Commit af398252 authored by Bhavya Kapoor's avatar Bhavya Kapoor Committed by Vignesh Raghavendra
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arm64: dts: ti: k3-j721e-main: Update delay select values for MMC subsystems 

Update the delay values for various speed modes supported, based on
the revised august 2021 J721E Datasheet.

[1] - Table 7-77. MMC0 DLL Delay Mapping for All Timing Modes and
Table 7-86. MMC1/2 DLL Delay Mapping for All Timing Modes, in
https://www.ti.com/lit/ds/symlink/tda4vm.pdf

,
(SPRSP36J – FEBRUARY 2019 – REVISED AUGUST 2021)

Signed-off-by: default avatarBhavya Kapoor <b-kapoor@ti.com>
Link: https://lore.kernel.org/r/20230424093827.1378602-1-b-kapoor@ti.com


Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
parent 5cab8aba

arch/arm64/boot/dts/ti/k3-j721e-main.dtsi

+6 −4
Original line number Diff line number Diff line
@@ -1287,8 +1287,8 @@ main_sdhci0: mmc@4f80000 { 
		bus-width = <8>;

		mmc-hs200-1_8v;

		mmc-ddr-1_8v;

		ti,otap-del-sel-legacy = <0xf>;

		ti,otap-del-sel-mmc-hs = <0xf>;

		ti,otap-del-sel-legacy = <0x0>;

		ti,otap-del-sel-mmc-hs = <0x0>;

		ti,otap-del-sel-ddr52 = <0x5>;

		ti,otap-del-sel-hs200 = <0x6>;

		ti,otap-del-sel-hs400 = <0x0>;
@@ -1309,11 +1309,12 @@ main_sdhci1: mmc@4fb0000 { 
		assigned-clocks = <&k3_clks 92 0>;

		assigned-clock-parents = <&k3_clks 92 1>;

		ti,otap-del-sel-legacy = <0x0>;

		ti,otap-del-sel-sd-hs = <0xf>;

		ti,otap-del-sel-sd-hs = <0x0>;

		ti,otap-del-sel-sdr12 = <0xf>;

		ti,otap-del-sel-sdr25 = <0xf>;

		ti,otap-del-sel-sdr50 = <0xc>;

		ti,otap-del-sel-ddr50 = <0xc>;

		ti,otap-del-sel-sdr104 = <0x5>;

		ti,itap-del-sel-legacy = <0x0>;

		ti,itap-del-sel-sd-hs = <0x0>;

		ti,itap-del-sel-sdr12 = <0x0>;
@@ -1335,11 +1336,12 @@ main_sdhci2: mmc@4f98000 { 
		assigned-clocks = <&k3_clks 93 0>;

		assigned-clock-parents = <&k3_clks 93 1>;

		ti,otap-del-sel-legacy = <0x0>;

		ti,otap-del-sel-sd-hs = <0xf>;

		ti,otap-del-sel-sd-hs = <0x0>;

		ti,otap-del-sel-sdr12 = <0xf>;

		ti,otap-del-sel-sdr25 = <0xf>;

		ti,otap-del-sel-sdr50 = <0xc>;

		ti,otap-del-sel-ddr50 = <0xc>;

		ti,otap-del-sel-sdr104 = <0x5>;

		ti,itap-del-sel-legacy = <0x0>;

		ti,itap-del-sel-sd-hs = <0x0>;

		ti,itap-del-sel-sdr12 = <0x0>;