Commit af571133 authored by William Qiu's avatar William Qiu Committed by Conor Dooley
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riscv: dts: starfive: add assigned-clock* to limit frquency 



In JH7110 SoC, we need to go by-pass mode, so we need add the
assigned-clock* properties to limit clock frquency.

Signed-off-by: default avatarWilliam Qiu <william.qiu@starfivetech.com>
Reviewed-by: default avatarEmil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent be326bee

arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -250,6 +250,8 @@ &i2stx1 { 


&mmc0 {

	max-frequency = <100000000>;

	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;

	assigned-clock-rates = <50000000>;

	bus-width = <8>;

	cap-mmc-highspeed;

	mmc-ddr-1_8v;
@@ -266,6 +268,8 @@ &mmc0 { 


&mmc1 {

	max-frequency = <100000000>;

	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;

	assigned-clock-rates = <50000000>;

	bus-width = <4>;

	no-sdio;

	no-mmc;