Commit afa91e2d authored by Ilya Bakoulin's avatar Ilya Bakoulin Committed by Alex Deucher
Browse files

drm/amd/display: Add 3DLUT DMA load trigger 



[Why/How]
Need to be able to trigger a DMA load to update 3DLUT contents in MPC.
Adding a HWSS function to serve as the trigger.

Reviewed-by: default avatarKrunoslav Kovac <krunoslav.kovac@amd.com>
Acked-by: default avatarRoman Li <roman.li@amd.com>
Signed-off-by: default avatarIlya Bakoulin <ilya.bakoulin@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ccb16710

drivers/gpu/drm/amd/display/dc/core/dc.c

+8 −0
Original line number Diff line number Diff line
@@ -4074,6 +4074,14 @@ static void commit_planes_for_stream(struct dc *dc, 
				if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))

					continue;



				if (srf_updates[i].cm2_params &&

						srf_updates[i].cm2_params->cm2_luts.lut3d_data.lut3d_src ==

								DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM &&

						srf_updates[i].cm2_params->component_settings.shaper_3dlut_setting ==

								DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT &&

						dc->hwss.trigger_3dlut_dma_load)

					dc->hwss.trigger_3dlut_dma_load(dc, pipe_ctx);



				/*program triple buffer after lock based on flip type*/

				if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {

					/*only enable triplebuffer for  fast_update*/

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

+13 −4
Original line number Diff line number Diff line
@@ -498,10 +498,10 @@ void dcn401_populate_mcm_luts(struct dc *dc, 
		if (m_lut_params.pwl) {

			if (mpc->funcs->populate_lut)

				mpc->funcs->populate_lut(mpc, MCM_LUT_1DLUT, m_lut_params, lut_bank_a, mpcc_id);

		}

		if (mpc->funcs->program_lut_mode)

			mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, lut1d_xable, lut_bank_a, mpcc_id);

	}

	}



	/* Shaper */

	if (mcm_luts.shaper) {
@@ -519,10 +519,10 @@ void dcn401_populate_mcm_luts(struct dc *dc, 
		if (m_lut_params.pwl) {

			if (mpc->funcs->populate_lut)

				mpc->funcs->populate_lut(mpc, MCM_LUT_SHAPER, m_lut_params, lut_bank_a, mpcc_id);

		}

		if (mpc->funcs->program_lut_mode)

			mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, shaper_xable, lut_bank_a, mpcc_id);

	}

	}



	/* 3DLUT */

	switch (lut3d_src) {
@@ -635,6 +635,15 @@ void dcn401_populate_mcm_luts(struct dc *dc, 
	}

}



void dcn401_trigger_3dlut_dma_load(struct dc *dc, struct pipe_ctx *pipe_ctx)

{

	struct hubp *hubp = pipe_ctx->plane_res.hubp;



	if (hubp->funcs->hubp_enable_3dlut_fl) {

		hubp->funcs->hubp_enable_3dlut_fl(hubp, true);

	}

}



bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,

				const struct dc_plane_state *plane_state)

{

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

+2 −0
Original line number Diff line number Diff line
@@ -40,6 +40,8 @@ bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx, 
bool dcn401_set_output_transfer_func(struct dc *dc,

				struct pipe_ctx *pipe_ctx,

				const struct dc_stream_state *stream);

void dcn401_trigger_3dlut_dma_load(struct dc *dc,

				struct pipe_ctx *pipe_ctx);

void dcn401_calculate_dccg_tmds_div_value(struct pipe_ctx *pipe_ctx,

				unsigned int *tmds_div);

enum dc_status dcn401_enable_stream_timing(

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c

+1 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ static const struct hw_sequencer_funcs dcn401_funcs = { 
	.update_dchub = dcn10_update_dchub,

	.update_pending_status = dcn10_update_pending_status,

	.program_output_csc = dcn20_program_output_csc,

	.trigger_3dlut_dma_load = dcn401_trigger_3dlut_dma_load,

	.enable_accelerated_mode = dce110_enable_accelerated_mode,

	.enable_timing_synchronization = dcn10_enable_timing_synchronization,

	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

+1 −0
Original line number Diff line number Diff line
@@ -304,6 +304,7 @@ struct hw_sequencer_funcs { 
	void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx,

			enum dc_color_space colorspace,

			uint16_t *matrix, int opp_id);

	void (*trigger_3dlut_dma_load)(struct dc *dc, struct pipe_ctx *pipe_ctx);



	/* VM Related */

	int (*init_sys_ctx)(struct dce_hwseq *hws,