Commit afc6053d authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

Reapply: drm/amdgpu: Use generic hdp flush function 



Except HDP v5.2 all use a common logic for HDP flush. Use a generic
function. HDP v5.2 forces NO_KIQ logic, revisit it later.

Reapply after fixing up an HDP regression.

v2: merge the fix (Alex)

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> (v1)
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent dbc064ad

drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c

+20 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
 */

#include "amdgpu.h"

#include "amdgpu_ras.h"

#include <uapi/linux/kfd_ioctl.h>



int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev)

{
@@ -46,3 +47,22 @@ int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev) 
	/* hdp ras follows amdgpu_ras_block_late_init_default for late init */

	return 0;

}



void amdgpu_hdp_generic_flush(struct amdgpu_device *adev,

			      struct amdgpu_ring *ring)

{

	if (!ring || !ring->funcs->emit_wreg) {

		WREG32((adev->rmmio_remap.reg_offset +

			KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >>

			       2,

		       0);

		if (adev->nbio.funcs->get_memsize)

			adev->nbio.funcs->get_memsize(adev);

	} else {

		amdgpu_ring_emit_wreg(ring,

				      (adev->rmmio_remap.reg_offset +

				       KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >>

					      2,

				      0);

	}

}

drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h

+2 −0
Original line number Diff line number Diff line
@@ -44,4 +44,6 @@ struct amdgpu_hdp { 
};



int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev);

void amdgpu_hdp_generic_flush(struct amdgpu_device *adev,

			      struct amdgpu_ring *ring);

#endif /* __AMDGPU_HDP_H__ */

drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c

+1 −17
Original line number Diff line number Diff line
@@ -36,22 +36,6 @@ 
#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK     0x00020000L

#define mmHDP_MEM_POWER_CTRL_BASE_IDX   0



static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,

				struct amdgpu_ring *ring)

{

	if (!ring || !ring->funcs->emit_wreg) {

		WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);

		/* We just need to read back a register to post the write.

		 * Reading back the remapped register causes problems on

		 * some platforms so just read back the memory size register.

		 */

		if (adev->nbio.funcs->get_memsize)

			adev->nbio.funcs->get_memsize(adev);

	} else {

		amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);

	}

}



static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,

				    struct amdgpu_ring *ring)

{
@@ -185,7 +169,7 @@ struct amdgpu_hdp_ras hdp_v4_0_ras = { 
};



const struct amdgpu_hdp_funcs hdp_v4_0_funcs = {

	.flush_hdp = hdp_v4_0_flush_hdp,

	.flush_hdp = amdgpu_hdp_generic_flush,

	.invalidate_hdp = hdp_v4_0_invalidate_hdp,

	.update_clock_gating = hdp_v4_0_update_clock_gating,

	.get_clock_gating_state = hdp_v4_0_get_clockgating_state,

drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

+1 −17
Original line number Diff line number Diff line
@@ -27,22 +27,6 @@ 
#include "hdp/hdp_5_0_0_sh_mask.h"

#include <uapi/linux/kfd_ioctl.h>



static void hdp_v5_0_flush_hdp(struct amdgpu_device *adev,

				struct amdgpu_ring *ring)

{

	if (!ring || !ring->funcs->emit_wreg) {

		WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);

		/* We just need to read back a register to post the write.

		 * Reading back the remapped register causes problems on

		 * some platforms so just read back the memory size register.

		 */

		if (adev->nbio.funcs->get_memsize)

			adev->nbio.funcs->get_memsize(adev);

	} else {

		amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);

	}

}



static void hdp_v5_0_invalidate_hdp(struct amdgpu_device *adev,

				    struct amdgpu_ring *ring)

{
@@ -222,7 +206,7 @@ static void hdp_v5_0_init_registers(struct amdgpu_device *adev) 
}



const struct amdgpu_hdp_funcs hdp_v5_0_funcs = {

	.flush_hdp = hdp_v5_0_flush_hdp,

	.flush_hdp = amdgpu_hdp_generic_flush,

	.invalidate_hdp = hdp_v5_0_invalidate_hdp,

	.update_clock_gating = hdp_v5_0_update_clock_gating,

	.get_clock_gating_state = hdp_v5_0_get_clockgating_state,

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

+1 −17
Original line number Diff line number Diff line
@@ -30,22 +30,6 @@ 
#define regHDP_CLK_CNTL_V6_1	0xd5

#define regHDP_CLK_CNTL_V6_1_BASE_IDX 0



static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev,

				struct amdgpu_ring *ring)

{

	if (!ring || !ring->funcs->emit_wreg) {

		WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);

		/* We just need to read back a register to post the write.

		 * Reading back the remapped register causes problems on

		 * some platforms so just read back the memory size register.

		 */

		if (adev->nbio.funcs->get_memsize)

			adev->nbio.funcs->get_memsize(adev);

	} else {

		amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);

	}

}



static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,

					 bool enable)

{
@@ -154,7 +138,7 @@ static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev, 
}



const struct amdgpu_hdp_funcs hdp_v6_0_funcs = {

	.flush_hdp = hdp_v6_0_flush_hdp,

	.flush_hdp = amdgpu_hdp_generic_flush,

	.update_clock_gating = hdp_v6_0_update_clock_gating,

	.get_clock_gating_state = hdp_v6_0_get_clockgating_state,

};