Commit afdfd829 authored by Luca Weiss's avatar Luca Weiss Committed by Bjorn Andersson
Browse files

clk: qcom: gcc-sm6350: Add *_wait_val values for GDSCs 



Compared to the msm-4.19 driver the mainline GDSC driver always sets the
bits for en_rest, en_few & clk_dis, and if those values are not set
per-GDSC in the respective driver then the default value from the GDSC
driver is used. The downstream driver only conditionally sets
clk_dis_wait_val if qcom,clk-dis-wait-val is given in devicetree.

Correct this situation by explicitly setting those values. For all GDSCs
the reset value of those bits are used.

Fixes: 131abae9 ("clk: qcom: Add SM6350 GCC driver")
Signed-off-by: default avatarLuca Weiss <luca.weiss@fairphone.com>
Reviewed-by: default avatarTaniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250425-sm6350-gdsc-val-v1-3-1f252d9c5e4e@fairphone.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 673989d2

drivers/clk/qcom/gcc-sm6350.c

+6 −0
Original line number Diff line number Diff line
@@ -2320,6 +2320,9 @@ static struct clk_branch gcc_video_xo_clk = { 


static struct gdsc usb30_prim_gdsc = {

	.gdscr = 0x1a004,

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "usb30_prim_gdsc",

	},
@@ -2328,6 +2331,9 @@ static struct gdsc usb30_prim_gdsc = { 


static struct gdsc ufs_phy_gdsc = {

	.gdscr = 0x3a004,

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "ufs_phy_gdsc",

	},