Commit b006ef5f authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-7.1-2026-04-30' of... 

Merge tag 'amd-drm-fixes-7.1-2026-04-30' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-7.1-2026-04-30:

amdgpu:
- GFX12 fix for CONFIG_DRM_DEBUG_MM configs
- Fix DC analog support
- Userq fixes
- GART placement fix
- Aldebaran SMU fixes
- AMDGPU_INFO_READ_MMR_REG fix
- UVD 3.1 fix
- GC 6 TCC fix
- Fix root reservation in amdgpu_vm_handle_fault()
- RAS fix
- Module reload fix for APUs
- Fix build for CONFIG_DRM_FBDEV_EMULATION=n
- IGT DWB regression fix
- GC 11.5.4 fix
- VCN user fence fixes
- JPEG user fence fixes
- SMU 13.0.6 fix
- VCN 3/4 IB parser fixes
- NV3x+ dGPU vblank fix
- DCE6/8 fixes for LVDS/eDP panels without an EDID

amdkfd:
- Fix for when CONFIG_HSA_AMD is not set
- SVM fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patch.msgid.link/20260430135619.3929877-1-alexander.deucher@amd.com
parents 39436e1d 019155e2

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+5 −1
Original line number Diff line number Diff line
@@ -2839,8 +2839,12 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) 
	 * that checks whether the PSP is running. A solution for those issues

	 * in the APU is to trigger a GPU reset, but this should be done during

	 * the unload phase to avoid adding boot latency and screen flicker.

	 * GFX V11 has GC block as default off IP. Every time AMDGPU driver sends

	 * a request to PMFW to unload MP1, PMFW will put GC in reset and power down

	 * the voltage. Hence, skipping reset for APUs with GFX V11 or later.

	 */

	if ((adev->flags & AMD_IS_APU) && !adev->gmc.is_app_apu) {

	if ((adev->flags & AMD_IS_APU) && !adev->gmc.is_app_apu &&

		amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(11, 0, 0)) {

		r = amdgpu_asic_reset(adev);

		if (r)

			dev_err(adev->dev, "asic reset on %s failed\n", __func__);

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

+1 −3
Original line number Diff line number Diff line
@@ -3090,10 +3090,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 
	case IP_VERSION(11, 5, 1):

	case IP_VERSION(11, 5, 2):

	case IP_VERSION(11, 5, 3):

		adev->family = AMDGPU_FAMILY_GC_11_5_0;

		break;

	case IP_VERSION(11, 5, 4):

		adev->family = AMDGPU_FAMILY_GC_11_5_4;

		adev->family = AMDGPU_FAMILY_GC_11_5_0;

		break;

	case IP_VERSION(12, 0, 0):

	case IP_VERSION(12, 0, 1):

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+4 −2
Original line number Diff line number Diff line
@@ -3158,8 +3158,10 @@ static int __init amdgpu_init(void) 
	amdgpu_register_atpx_handler();

	amdgpu_acpi_detect();



	/* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */

	amdgpu_amdkfd_init();

	/* Ignore KFD init failures when CONFIG_HSA_AMD is not set. */

	r = amdgpu_amdkfd_init();

	if (r && r != -ENOENT)

		goto error_fence;



	if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) {

		add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

+4 −1
Original line number Diff line number Diff line
@@ -314,7 +314,10 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 
		mc->gart_start = max_mc_address - mc->gart_size + 1;

		break;

	case AMDGPU_GART_PLACEMENT_LOW:

		if (size_bf >= mc->gart_size)

			mc->gart_start = 0;

		else

			mc->gart_start = ALIGN(mc->fb_end, four_gb);

		break;

	case AMDGPU_GART_PLACEMENT_BEST_FIT:

	default:

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+24 −33
Original line number Diff line number Diff line
@@ -873,68 +873,59 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 
				    ? -EFAULT : 0;

	}

	case AMDGPU_INFO_READ_MMR_REG: {

		int ret = 0;

		unsigned int n, alloc_size;

		uint32_t *regs;

		unsigned int se_num = (info->read_mmr_reg.instance >>

				   AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &

				  AMDGPU_INFO_MMR_SE_INDEX_MASK;

		unsigned int sh_num = (info->read_mmr_reg.instance >>

				   AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &

				  AMDGPU_INFO_MMR_SH_INDEX_MASK;



		if (!down_read_trylock(&adev->reset_domain->sem))

			return -ENOENT;

		unsigned int alloc_size;

		uint32_t *regs;

		int ret;



		/* set full masks if the userspace set all bits

		 * in the bitfields

		 */

		if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) {

		if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)

			se_num = 0xffffffff;

		} else if (se_num >= AMDGPU_GFX_MAX_SE) {

			ret = -EINVAL;

			goto out;

		}

		else if (se_num >= AMDGPU_GFX_MAX_SE)

			return -EINVAL;



		if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) {

		if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)

			sh_num = 0xffffffff;

		} else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) {

			ret = -EINVAL;

			goto out;

		}

		else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)

			return -EINVAL;



		if (info->read_mmr_reg.count > 128) {

			ret = -EINVAL;

			goto out;

		}

		if (info->read_mmr_reg.count > 128)

			return -EINVAL;



		regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);

		if (!regs) {

			ret = -ENOMEM;

			goto out;

		}

		regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs),

				     GFP_KERNEL);

		if (!regs)

			return -ENOMEM;



		down_read(&adev->reset_domain->sem);

		alloc_size = info->read_mmr_reg.count * sizeof(*regs);



		amdgpu_gfx_off_ctrl(adev, false);

		ret = 0;

		for (i = 0; i < info->read_mmr_reg.count; i++) {

			if (amdgpu_asic_read_register(adev, se_num, sh_num,

						      info->read_mmr_reg.dword_offset + i,

						      &regs[i])) {

				DRM_DEBUG_KMS("unallowed offset %#x\n",

					      info->read_mmr_reg.dword_offset + i);

				kfree(regs);

				amdgpu_gfx_off_ctrl(adev, true);

				ret = -EFAULT;

				goto out;

				break;

			}

		}

		amdgpu_gfx_off_ctrl(adev, true);

		n = copy_to_user(out, regs, min(size, alloc_size));

		kfree(regs);

		ret = (n ? -EFAULT : 0);

out:

		up_read(&adev->reset_domain->sem);



		if (!ret) {

			ret = copy_to_user(out, regs, min(size, alloc_size))

				? -EFAULT : 0;

		}

		kfree(regs);

		return ret;

	}

	case AMDGPU_INFO_DEV_INFO: {