Commit b01bf907 authored by Stephen Boyd's avatar Stephen Boyd
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Merge tag 'renesas-clk-for-v6.12-tag1' of... 

Merge tag 'renesas-clk-for-v6.12-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven

 - Add PCIe, PWM, and CAN-FD clocks on R-Car V4M
 - Add LCD controller clocks and resets on RZ/G2UL
 - Add DMA clocks and resets on RZ/G3S
 - Add fractional multiplication PLL support on R-Car Gen4
 - Document support for the Renesas RZ/G2M v3.0 (r8a774a3) SoC
 - Add support for the RZ/V2H(P) (R9A09G057) SoC
 - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v6.12-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (30 commits)
  clk: renesas: r8a779h0: Add CANFD clock
  clk: renesas: Add RZ/V2H(P) CPG driver
  clk: renesas: Add family-specific clock driver for RZ/V2H(P)
  dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG
  clk: renesas: r8a779h0: Add PWM clock
  dt-bindings: clock: renesas,cpg-mssr: Document RZ/G2M v3.0 (r8a774a3) clock
  clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs
  clk: renesas: rcar-gen4: Remove unused fixed PLL clock types
  clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type
  clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs
  clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLs
  clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLs
  clk: renesas: r8a779a0: Use defines for PLL control registers
  clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs
  clk: renesas: rcar-gen4: Add support for fixed variable PLLs
  clk: renesas: rcar-gen4: Add support for variable fractional PLLs
  clk: renesas: rcar-gen4: Add support for fractional multiplication
  clk: renesas: rcar-gen4: Use defines for common CPG registers
  clk: renesas: rcar-gen4: Use FIELD_GET()
  clk: renesas: rcar-gen4: Clarify custom PLL clock support
  ...
parents 8400291e 120c2833

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml

+1 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ properties: 
      - renesas,r8a7745-cpg-mssr  # RZ/G1E

      - renesas,r8a77470-cpg-mssr # RZ/G1C

      - renesas,r8a774a1-cpg-mssr # RZ/G2M

      - renesas,r8a774a3-cpg-mssr # RZ/G2M v3.0

      - renesas,r8a774b1-cpg-mssr # RZ/G2N

      - renesas,r8a774c0-cpg-mssr # RZ/G2E

      - renesas,r8a774e1-cpg-mssr # RZ/G2H

Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml

0 → 100644
+80 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)



maintainers:

  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>



description:

  On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation

  and control of clock signals for the IP modules, generation and control of resets,

  and control over booting, low power consumption and power supply domains.



properties:

  compatible:

    const: renesas,r9a09g057-cpg



  reg:

    maxItems: 1



  clocks:

    items:

      - description: AUDIO_EXTAL clock input

      - description: RTXIN clock input

      - description: QEXTAL clock input



  clock-names:

    items:

      - const: audio_extal

      - const: rtxin

      - const: qextal



  '#clock-cells':

    description: |

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

        and a core clock reference, as defined in

        <dt-bindings/clock/renesas,r9a09g057-cpg.h>,

      - For module clocks, the two clock specifier cells must be "CPG_MOD" and

        a module number.  The module number is calculated as the CLKON register

        offset index multiplied by 16, plus the actual bit in the register

        used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the

        calculation is (1 * 16 + 3) = 0x13.

    const: 2



  '#power-domain-cells':

    const: 0



  '#reset-cells':

    description:

      The single reset specifier cell must be the reset number. The reset number

      is calculated as the reset register offset index multiplied by 16, plus the

      actual bit in the register used to reset the specific IP block. For example,

      for SYS_0_PRESETN, the calculation is (3 * 16 + 0) = 0x30.

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#power-domain-cells'

  - '#reset-cells'



additionalProperties: false



examples:

  - |

    clock-controller@10420000 {

        compatible = "renesas,r9a09g057-cpg";

        reg = <0x10420000 0x10000>;

        clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;

        clock-names = "audio_extal", "rtxin", "qextal";

        #clock-cells = <2>;

        #power-domain-cells = <0>;

        #reset-cells = <1>;

    };

drivers/clk/renesas/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ config CLK_RENESAS 
	select CLK_R9A07G054 if ARCH_R9A07G054

	select CLK_R9A08G045 if ARCH_R9A08G045

	select CLK_R9A09G011 if ARCH_R9A09G011

	select CLK_R9A09G057 if ARCH_R9A09G057

	select CLK_SH73A0 if ARCH_SH73A0



if CLK_RENESAS
@@ -193,6 +194,10 @@ config CLK_R9A09G011 
	bool "RZ/V2M clock support" if COMPILE_TEST

	select CLK_RZG2L



config CLK_R9A09G057

       bool "RZ/V2H(P) clock support" if COMPILE_TEST

       select CLK_RZV2H



config CLK_SH73A0

	bool "SH-Mobile AG5 clock support" if COMPILE_TEST

	select CLK_RENESAS_CPG_MSTP
@@ -228,6 +233,10 @@ config CLK_RZG2L 
	bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST

	select RESET_CONTROLLER



config CLK_RZV2H

	bool "RZ/V2H(P) family clock support" if COMPILE_TEST

	select RESET_CONTROLLER



# Generic

config CLK_RENESAS_CPG_MSSR

	bool "CPG/MSSR clock support" if COMPILE_TEST

drivers/clk/renesas/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o 
obj-$(CONFIG_CLK_R9A07G054)		+= r9a07g044-cpg.o

obj-$(CONFIG_CLK_R9A08G045)		+= r9a08g045-cpg.o

obj-$(CONFIG_CLK_R9A09G011)		+= r9a09g011-cpg.o

obj-$(CONFIG_CLK_R9A09G057)		+= r9a09g057-cpg.o

obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o



# Family
@@ -46,6 +47,7 @@ obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o 
obj-$(CONFIG_CLK_RCAR_GEN4_CPG)		+= rcar-gen4-cpg.o

obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL)	+= rcar-usb2-clock-sel.o

obj-$(CONFIG_CLK_RZG2L)			+= rzg2l-cpg.o

obj-$(CONFIG_CLK_RZV2H)			+= rzv2h-cpg.o



# Generic

obj-$(CONFIG_CLK_RENESAS_CPG_MSSR)	+= renesas-cpg-mssr.o

drivers/clk/renesas/r8a779a0-cpg-mssr.c

+21 −16
Original line number Diff line number Diff line
@@ -61,6 +61,11 @@ enum clk_ids { 
	DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \

		 .offset = _offset)



#define CPG_PLL20CR	0x0834	/* PLL20 Control Register */

#define CPG_PLL21CR	0x0838	/* PLL21 Control Register */

#define CPG_PLL30CR	0x083c	/* PLL30 Control Register */

#define CPG_PLL31CR	0x0840	/* PLL31 Control Register */



static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {

	/* External Clock Inputs */

	DEF_INPUT("extal",  CLK_EXTAL),
@@ -70,10 +75,10 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 
	DEF_BASE(".main", CLK_MAIN,	CLK_TYPE_GEN4_MAIN, CLK_EXTAL),

	DEF_BASE(".pll1", CLK_PLL1,	CLK_TYPE_GEN4_PLL1, CLK_MAIN),

	DEF_BASE(".pll5", CLK_PLL5,	CLK_TYPE_GEN4_PLL5, CLK_MAIN),

	DEF_PLL(".pll20", CLK_PLL20,	0x0834),

	DEF_PLL(".pll21", CLK_PLL21,	0x0838),

	DEF_PLL(".pll30", CLK_PLL30,	0x083c),

	DEF_PLL(".pll31", CLK_PLL31,	0x0840),

	DEF_PLL(".pll20", CLK_PLL20,	CPG_PLL20CR),

	DEF_PLL(".pll21", CLK_PLL21,	CPG_PLL21CR),

	DEF_PLL(".pll30", CLK_PLL30,	CPG_PLL30CR),

	DEF_PLL(".pll31", CLK_PLL31,	CPG_PLL31CR),



	DEF_FIXED(".pll1_div2",		CLK_PLL1_DIV2,	CLK_PLL1,	2, 1),

	DEF_FIXED(".pll20_div2",	CLK_PLL20_DIV2,	CLK_PLL20,	2, 1),
@@ -116,17 +121,17 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 
	DEF_FIXED("cp",		R8A779A0_CLK_CP,	CLK_EXTAL,	2, 1),

	DEF_FIXED("cl16mck",	R8A779A0_CLK_CL16MCK,	CLK_PLL1_DIV2,	64, 1),



	DEF_GEN4_SDH("sd0h",	R8A779A0_CLK_SD0H,	CLK_SDSRC,	   0x870),

	DEF_GEN4_SD("sd0",	R8A779A0_CLK_SD0,	R8A779A0_CLK_SD0H, 0x870),

	DEF_GEN4_SDH("sd0h",	R8A779A0_CLK_SD0H,	CLK_SDSRC,	   CPG_SD0CKCR),

	DEF_GEN4_SD("sd0",	R8A779A0_CLK_SD0,	R8A779A0_CLK_SD0H, CPG_SD0CKCR),



	DEF_BASE("rpc",		R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),

	DEF_BASE("rpcd2",	R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2,

		 R8A779A0_CLK_RPC),



	DEF_DIV6P1("mso",	R8A779A0_CLK_MSO,	CLK_PLL5_DIV4,	0x87c),

	DEF_DIV6P1("canfd",	R8A779A0_CLK_CANFD,	CLK_PLL5_DIV4,	0x878),

	DEF_DIV6P1("csi0",	R8A779A0_CLK_CSI0,	CLK_PLL5_DIV4,	0x880),

	DEF_DIV6P1("dsi",	R8A779A0_CLK_DSI,	CLK_PLL5_DIV4,	0x884),

	DEF_DIV6P1("mso",	R8A779A0_CLK_MSO,	CLK_PLL5_DIV4,	CPG_MSOCKCR),

	DEF_DIV6P1("canfd",	R8A779A0_CLK_CANFD,	CLK_PLL5_DIV4,	CPG_CANFDCKCR),

	DEF_DIV6P1("csi0",	R8A779A0_CLK_CSI0,	CLK_PLL5_DIV4,	CPG_CSICKCR),

	DEF_DIV6P1("dsi",	R8A779A0_CLK_DSI,	CLK_PLL5_DIV4,	CPG_DSIEXTCKCR),



	DEF_GEN4_OSC("osc",	R8A779A0_CLK_OSC,	CLK_EXTAL,	8),

	DEF_GEN4_MDSEL("r",	R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
@@ -253,12 +258,12 @@ static const unsigned int r8a779a0_crit_mod_clks[] __initconst = { 
 */

#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 13) | \

					 (((md) & BIT(13)) >> 13))

static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {

	/* EXTAL div	PLL1 mult/div	PLL2 mult/div	PLL3 mult/div	PLL4 mult/div	PLL5 mult/div	PLL6 mult/div	OSC prediv */

	{ 1,		128,	1,	0,	0,	0,	0,	144,	1,	192,	1,	0,	0,	16,	},

	{ 1,		106,	1,	0,	0,	0,	0,	120,	1,	160,	1,	0,	0,	19,	},

	{ 0,		0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	},

	{ 2,		128,	1,	0,	0,	0,	0,	144,	1,	192,	1,	0,	0,	32,	},

static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] __initconst = {

	/* EXTAL div	PLL1 mult/div	PLL5 mult/div	OSC prediv */

	{ 1,		128,	1,	192,	1,	16,	},

	{ 1,		106,	1,	160,	1,	19,	},

	{ 0,		0,	0,	0,	0,	0,	},

	{ 2,		128,	1,	192,	1,	32,	},

};