Commit b02c9b5e authored by Imre Deak's avatar Imre Deak Committed by Mika Kahola
Browse files

drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_HDMI_FRL flag macro 



Define PHY_C20_IS_HDMI_FRL, so it can be used instead of the plain bit number.

Reviewed-by: default avatarLuca Coelho <luciano.coelho@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarMika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20251015125446.3931198-5-mika.kahola@intel.com
parent a1792df6

drivers/gpu/drm/i915/display/intel_cx0_phy.c

+2 −2
Original line number Diff line number Diff line
@@ -2706,8 +2706,8 @@ static void intel_c20_pll_program(struct intel_display *display, 
			      MB_WRITE_COMMITTED);

	} else {

		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,

			      BIT(7) | PHY_C20_DP_RATE_MASK,

			      is_hdmi_frl(port_clock) ? BIT(7) : 0,

			      PHY_C20_IS_HDMI_FRL | PHY_C20_DP_RATE_MASK,

			      is_hdmi_frl(port_clock) ? PHY_C20_IS_HDMI_FRL : 0,

			      MB_WRITE_COMMITTED);



		intel_cx0_write(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -298,6 +298,7 @@ 
#define PHY_C20_RD_DATA_L		0xC08

#define PHY_C20_RD_DATA_H		0xC09

#define PHY_C20_VDR_CUSTOM_SERDES_RATE	0xD00

#define   PHY_C20_IS_HDMI_FRL		REG_BIT8(7)

#define   PHY_C20_IS_DP			REG_BIT8(6)

#define   PHY_C20_DP_RATE_MASK		REG_GENMASK8(4, 1)

#define   PHY_C20_DP_RATE(val)		REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val)