Commit b074c5e6 authored by Daniel Machon's avatar Daniel Machon Committed by Jakub Kicinski
Browse files

net: sparx5: use is_sparx5() macro throughout 

Use the is_sparx5() macro (introduced in earlier series [1]), in places
where we need to handle things a bit differently on lan969x.

These places are:

    - in sparx5_dsm_calendar_update() we need to switch the calendar
      from a to b on lan969x.

    - in sparx5_start() we need to make sure the HSCH_SYS_CLK_PER
      register is only touched on Sparx5.

    - in sparx5_start() we need to disable VCAP and FDMA for lan969x
      (will come in later series).

    - in sparx5_mirror_port_get() we must make sure the
      ANA_AC_PROBE_PORT_CFG1 register is only read on Sparx5.

    - sparx5_netdev.c and sparx5_packet.c we need to use different IFH
      (Internal Frame Header) offsets for lan969x.

    - in sparx5_port_fifo_sz() we must bail out on lan969x.

    - in sparx5_port_config_low_set() we must configure the phase
      detection registers.

    - in sparx5_port_config() and sparx5_port_init() we must do some
      additional configuration of the port devices.

    - in sparx5_dwrr_conf_set() we must derive the scheduling layer

[1] https://lore.kernel.org/netdev/20241004-b4-sparx5-lan969x-switch-driver-v2-8-d3290f581663@microchip.com/



Reviewed-by: default avatarSteen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: default avatarDaniel Machon <daniel.machon@microchip.com>
Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-12-a0b5fae88a0f@microchip.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 5d2ba394

drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c

+19 −2
Original line number Diff line number Diff line
@@ -531,8 +531,18 @@ static int sparx5_dsm_calendar_check(struct sparx5 *sparx5, 
static int sparx5_dsm_calendar_update(struct sparx5 *sparx5, u32 taxi,

				      struct sparx5_calendar_data *data)

{

	u32 idx;

	u32 cal_len = sparx5_dsm_cal_len(data->schedule), len;

	u32 cal_len = sparx5_dsm_cal_len(data->schedule), len, idx;



	if (!is_sparx5(sparx5)) {

		u32 val, act;



		val = spx5_rd(sparx5, DSM_TAXI_CAL_CFG(taxi));

		act = DSM_TAXI_CAL_CFG_CAL_SEL_STAT_GET(val);



		spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(!act),

			 DSM_TAXI_CAL_CFG_CAL_PGM_SEL,

			 sparx5, DSM_TAXI_CAL_CFG(taxi));

	}



	spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1),

		 DSM_TAXI_CAL_CFG_CAL_PGM_ENA,
@@ -556,6 +566,13 @@ static int sparx5_dsm_calendar_update(struct sparx5 *sparx5, u32 taxi, 
						       DSM_TAXI_CAL_CFG(taxi)));

	if (len != cal_len - 1)

		goto update_err;



	if (!is_sparx5(sparx5)) {

		spx5_rmw(DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(1),

			 DSM_TAXI_CAL_CFG_CAL_SWITCH,

			 sparx5, DSM_TAXI_CAL_CFG(taxi));

	}



	return 0;

update_err:

	dev_err(sparx5->dev, "Incorrect calendar length: %u\n", len);

drivers/net/ethernet/microchip/sparx5/sparx5_main.c

+12 −9
Original line number Diff line number Diff line
@@ -538,6 +538,7 @@ static int sparx5_init_coreclock(struct sparx5 *sparx5) 
	sparx5->coreclock = freq;

	clk_period = sparx5_clk_period(freq);



	if (is_sparx5(sparx5))

		spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100),

			 HSCH_SYS_CLK_PER_100PS,

			 sparx5,
@@ -731,15 +732,17 @@ static int sparx5_start(struct sparx5 *sparx5) 
	if (err)

		return err;



	if (is_sparx5(sparx5)) {

		err = sparx5_vcap_init(sparx5);

		if (err) {

			sparx5_unregister_notifier_blocks(sparx5);

			return err;

		}

	}



	/* Start Frame DMA with fallback to register based INJ/XTR */

	err = -ENXIO;

	if (sparx5->fdma_irq >= 0) {

	if (sparx5->fdma_irq >= 0 && is_sparx5(sparx5)) {

		if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0)

			err = devm_request_threaded_irq(sparx5->dev,

							sparx5->fdma_irq,

drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c

+8 −2
Original line number Diff line number Diff line
@@ -24,8 +24,14 @@ static u32 sparx5_mirror_to_dir(bool ingress) 
/* Get ports belonging to this mirror */

static u64 sparx5_mirror_port_get(struct sparx5 *sparx5, u32 idx)

{

	return (u64)spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG1(idx)) << 32 |

	       spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG(idx));

	u64 val;



	val = spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG(idx));



	if (is_sparx5(sparx5))

		val |= (u64)spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG1(idx)) << 32;



	return val;

}



/* Add port to mirror (only front ports) */

drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c

+10 −7
Original line number Diff line number Diff line
@@ -64,16 +64,16 @@ void sparx5_set_port_ifh(struct sparx5 *sparx5, void *ifh_hdr, u16 portno) 
	/* MISC.CPU_MASK/DPORT = Destination port */

	ifh_encode_bitfield(ifh_hdr, portno,   29, 8);

	/* MISC.PIPELINE_PT */

	ifh_encode_bitfield(ifh_hdr, 16,       37, 5);

	ifh_encode_bitfield(ifh_hdr, is_sparx5(sparx5) ? 16 : 17, 37, 5);

	/* MISC.PIPELINE_ACT */

	ifh_encode_bitfield(ifh_hdr, 1,        42, 3);

	/* FWD.SRC_PORT = CPU */

	ifh_encode_bitfield(ifh_hdr, sparx5_get_pgid(sparx5, SPX5_PORT_CPU_0),

			    46, 7);

			    46, is_sparx5(sparx5) ? 7 : 6);

	/* FWD.SFLOW_ID (disable SFlow sampling) */

	ifh_encode_bitfield(ifh_hdr, 124,      57, 7);

	ifh_encode_bitfield(ifh_hdr, 124,      is_sparx5(sparx5) ? 57 : 56, 7);

	/* FWD.UPDATE_FCS = Enable. Enforce update of FCS. */

	ifh_encode_bitfield(ifh_hdr, 1,        67, 1);

	ifh_encode_bitfield(ifh_hdr, 1,        is_sparx5(sparx5) ? 67 : 66, 1);

}



void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op)
@@ -84,19 +84,22 @@ void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op) 
void sparx5_set_port_ifh_pdu_type(struct sparx5 *sparx5, void *ifh_hdr,

				  u32 pdu_type)

{

	ifh_encode_bitfield(ifh_hdr, pdu_type, 191, 4);

	ifh_encode_bitfield(ifh_hdr, pdu_type, is_sparx5(sparx5) ? 191 : 190,

			    4);

}



void sparx5_set_port_ifh_pdu_w16_offset(struct sparx5 *sparx5, void *ifh_hdr,

					u32 pdu_w16_offset)

{

	ifh_encode_bitfield(ifh_hdr, pdu_w16_offset, 195, 6);

	ifh_encode_bitfield(ifh_hdr, pdu_w16_offset,

			    is_sparx5(sparx5) ? 195 : 194, 6);

}



void sparx5_set_port_ifh_timestamp(struct sparx5 *sparx5, void *ifh_hdr,

				   u64 timestamp)

{

	ifh_encode_bitfield(ifh_hdr, timestamp, 232,  40);

	ifh_encode_bitfield(ifh_hdr, timestamp, 232,

			    is_sparx5(sparx5) ? 40 : 38);

}



static int sparx5_port_open(struct net_device *ndev)

drivers/net/ethernet/microchip/sparx5/sparx5_packet.c

+2 −1
Original line number Diff line number Diff line
@@ -43,7 +43,8 @@ void sparx5_ifh_parse(struct sparx5 *sparx5, u32 *ifh, struct frame_info *info) 
		((u32)xtr_hdr[29] <<  8) |

		((u32)xtr_hdr[30] <<  0);

	fwd = (fwd >> 5);

	info->src_port = FIELD_GET(GENMASK(7, 1), fwd);

	info->src_port = spx5_field_get(GENMASK(is_sparx5(sparx5) ? 7 : 6, 1),

					fwd);



	/*

	 * Bit 270-271 are occasionally unexpectedly set by the hardware,