Commit b0c5cf4f authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio
Browse files

drm/gt/guc: extract scheduler-related defines from guc_fwif.h 



Some upcoming KLVs are sized based on the engine counts, so we need
those defines to be moved to a separate file to include them from
guc_klv_abi.h (which is already included by guc_fwif.h).
Instead of moving just the engine-related defines, it is cleaner to
move all scheduler-related defines (i.e., everything engine or context
related). Note that the legacy GuC defines have not been moved and have
instead been dropped because Xe doesn't support any GuC old enough to
still use them.

While at it, struct guc_ctxt_registration_info has been moved to
guc_submit.c since it doesn't come from the GuC specs (we added it to
make things simpler in our code).

Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Link: https://patch.msgid.link/20251218223846.1146344-16-daniele.ceraolospurio@intel.com
parent 8d87fa19

drivers/gpu/drm/xe/abi/guc_scheduler_abi.h

0 → 100644
+48 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT */

/*

 * Copyright © 2025 Intel Corporation

 */



#ifndef _ABI_GUC_SCHEDULER_ABI_H

#define _ABI_GUC_SCHEDULER_ABI_H



/**

 * Generic defines required for registration with and submissions to the GuC

 * scheduler. Includes engine class/instance defines and context attributes

 * (id, priority, etc)

 */



/* Engine classes/instances */

#define GUC_RENDER_CLASS		0

#define GUC_VIDEO_CLASS			1

#define GUC_VIDEOENHANCE_CLASS		2

#define GUC_BLITTER_CLASS		3

#define GUC_COMPUTE_CLASS		4

#define GUC_GSC_OTHER_CLASS		5

#define GUC_LAST_ENGINE_CLASS		GUC_GSC_OTHER_CLASS

#define GUC_MAX_ENGINE_CLASSES		16

#define GUC_MAX_INSTANCES_PER_CLASS	32



/* context priority values */

#define GUC_CLIENT_PRIORITY_KMD_HIGH	0

#define GUC_CLIENT_PRIORITY_HIGH	1

#define GUC_CLIENT_PRIORITY_KMD_NORMAL	2

#define GUC_CLIENT_PRIORITY_NORMAL	3

#define GUC_CLIENT_PRIORITY_NUM		4



/* Context registration */

#define GUC_ID_MAX			65535

#define GUC_ID_UNKNOWN			0xffffffff



#define CONTEXT_REGISTRATION_FLAG_KMD	        BIT(0)

#define CONTEXT_REGISTRATION_FLAG_TYPE	        GENMASK(2, 1)

#define   GUC_CONTEXT_NORMAL			0

#define   GUC_CONTEXT_COMPRESSION_SAVE		1

#define   GUC_CONTEXT_COMPRESSION_RESTORE	2

#define   GUC_CONTEXT_COUNT			(GUC_CONTEXT_COMPRESSION_RESTORE + 1)



/* context enable/disable */

#define GUC_CONTEXT_DISABLE		0

#define GUC_CONTEXT_ENABLE		1



#endif

drivers/gpu/drm/xe/xe_guc_capture.h

+1 −1
Original line number Diff line number Diff line
@@ -8,8 +8,8 @@ 


#include <linux/types.h>

#include "abi/guc_capture_abi.h"

#include "abi/guc_scheduler_abi.h"

#include "xe_guc.h"

#include "xe_guc_fwif.h"



struct xe_exec_queue;

struct xe_guc;

drivers/gpu/drm/xe/xe_guc_fwif.h

+1 −53
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 


#include "abi/guc_capture_abi.h"

#include "abi/guc_klvs_abi.h"

#include "abi/guc_scheduler_abi.h"

#include "xe_hw_engine_types.h"



#define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET	4
@@ -19,59 +20,6 @@ 
#define G2H_LEN_DW_MULTI_QUEUE_CONTEXT		3

#define G2H_LEN_DW_PAGE_RECLAMATION		3



#define GUC_ID_MAX			65535

#define GUC_ID_UNKNOWN			0xffffffff



#define GUC_CONTEXT_DISABLE		0

#define GUC_CONTEXT_ENABLE		1



#define GUC_CLIENT_PRIORITY_KMD_HIGH	0

#define GUC_CLIENT_PRIORITY_HIGH	1

#define GUC_CLIENT_PRIORITY_KMD_NORMAL	2

#define GUC_CLIENT_PRIORITY_NORMAL	3

#define GUC_CLIENT_PRIORITY_NUM		4



#define GUC_RENDER_ENGINE		0

#define GUC_VIDEO_ENGINE		1

#define GUC_BLITTER_ENGINE		2

#define GUC_VIDEOENHANCE_ENGINE		3

#define GUC_VIDEO_ENGINE2		4

#define GUC_MAX_ENGINES_NUM		(GUC_VIDEO_ENGINE2 + 1)



#define GUC_RENDER_CLASS		0

#define GUC_VIDEO_CLASS			1

#define GUC_VIDEOENHANCE_CLASS		2

#define GUC_BLITTER_CLASS		3

#define GUC_COMPUTE_CLASS		4

#define GUC_GSC_OTHER_CLASS		5

#define GUC_LAST_ENGINE_CLASS		GUC_GSC_OTHER_CLASS

#define GUC_MAX_ENGINE_CLASSES		16

#define GUC_MAX_INSTANCES_PER_CLASS	32



#define GUC_CONTEXT_NORMAL			0

#define GUC_CONTEXT_COMPRESSION_SAVE		1

#define GUC_CONTEXT_COMPRESSION_RESTORE	2

#define GUC_CONTEXT_COUNT			(GUC_CONTEXT_COMPRESSION_RESTORE + 1)



/* Helper for context registration H2G */

struct guc_ctxt_registration_info {

	u32 flags;

	u32 context_idx;

	u32 engine_class;

	u32 engine_submit_mask;

	u32 wq_desc_lo;

	u32 wq_desc_hi;

	u32 wq_base_lo;

	u32 wq_base_hi;

	u32 wq_size;

	u32 cgp_lo;

	u32 cgp_hi;

	u32 hwlrca_lo;

	u32 hwlrca_hi;

};

#define CONTEXT_REGISTRATION_FLAG_KMD	BIT(0)

#define CONTEXT_REGISTRATION_FLAG_TYPE	GENMASK(2, 1)



/* 32-bit KLV structure as used by policy updates and others */

struct guc_klv_generic_dw_t {

	u32 kl;

drivers/gpu/drm/xe/xe_guc_submit.c

+17 −0
Original line number Diff line number Diff line
@@ -673,6 +673,23 @@ static void set_exec_queue_group_banned(struct xe_exec_queue *q) 
	mutex_unlock(&group->list_lock);

}



/* Helper for context registration H2G */

struct guc_ctxt_registration_info {

	u32 flags;

	u32 context_idx;

	u32 engine_class;

	u32 engine_submit_mask;

	u32 wq_desc_lo;

	u32 wq_desc_hi;

	u32 wq_base_lo;

	u32 wq_base_hi;

	u32 wq_size;

	u32 cgp_lo;

	u32 cgp_hi;

	u32 hwlrca_lo;

	u32 hwlrca_hi;

};



#define parallel_read(xe_, map_, field_) \

	xe_map_rd_field(xe_, &map_, 0, struct guc_submit_parallel_scratch, \

			field_)