Commit b0d011d4 authored by Jacky Bai's avatar Jacky Bai Committed by Shawn Guo
Browse files

arm64: dts: freescale: Add basic dtsi for imx943 



Add the minimal dtsi support for i.MX943. i.MX943 is the first SoC of
i.MX94 Family, create a common dtsi for the whole i.MX94 family, and the
specific dtsi part for i.MX943.

The clock, power domain and perf index need to be used by the device nodes
for resource reference, add them along with the dtsi support.

Signed-off-by: default avatarJacky Bai <ping.bai@nxp.com>
Reviewed-by: default avatarFrank Li <Frank.Li@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent a5042430

arch/arm64/boot/dts/freescale/imx94-clock.h

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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */

/*

 * Copyright 2024-2025 NXP

 */



#ifndef __IMX94_CLOCK_H

#define __IMX94_CLOCK_H



#define IMX94_CLK_EXT				0

#define IMX94_CLK_32K				1

#define IMX94_CLK_24M				2

#define IMX94_CLK_FRO				3

#define IMX94_CLK_SYSPLL1_VCO			4

#define IMX94_CLK_SYSPLL1_PFD0_UNGATED		5

#define IMX94_CLK_SYSPLL1_PFD0			6

#define IMX94_CLK_SYSPLL1_PFD0_DIV2		7

#define IMX94_CLK_SYSPLL1_PFD1_UNGATED		8

#define IMX94_CLK_SYSPLL1_PFD1			9

#define IMX94_CLK_SYSPLL1_PFD1_DIV2		10

#define IMX94_CLK_SYSPLL1_PFD2_UNGATED		11

#define IMX94_CLK_SYSPLL1_PFD2			12

#define IMX94_CLK_SYSPLL1_PFD2_DIV2		13

#define IMX94_CLK_AUDIOPLL1_VCO			14

#define IMX94_CLK_AUDIOPLL1			15

#define IMX94_CLK_AUDIOPLL2_VCO			16

#define IMX94_CLK_AUDIOPLL2			17

#define IMX94_CLK_RESERVED18			18

#define IMX94_CLK_RESERVED19			19

#define IMX94_CLK_RESERVED20			20

#define IMX94_CLK_RESERVED21			21

#define IMX94_CLK_RESERVED22			22

#define IMX94_CLK_RESERVED23			23

#define IMX94_CLK_ENCPLL_VCO			24

#define IMX94_CLK_ENCPLL_PFD0_UNGATED		25

#define IMX94_CLK_ENCPLL_PFD0			26

#define IMX94_CLK_ENCPLL_PFD1_UNGATED		27

#define IMX94_CLK_ENCPLL_PFD1			28

#define IMX94_CLK_ARMPLL_VCO			29

#define IMX94_CLK_ARMPLL_PFD0_UNGATED		30

#define IMX94_CLK_ARMPLL_PFD0			31

#define IMX94_CLK_ARMPLL_PFD1_UNGATED		32

#define IMX94_CLK_ARMPLL_PFD1			33

#define IMX94_CLK_ARMPLL_PFD2_UNGATED		34

#define IMX94_CLK_ARMPLL_PFD2			35

#define IMX94_CLK_ARMPLL_PFD3_UNGATED		36

#define IMX94_CLK_ARMPLL_PFD3			37

#define IMX94_CLK_DRAMPLL_VCO			38

#define IMX94_CLK_DRAMPLL			39

#define IMX94_CLK_HSIOPLL_VCO			40

#define IMX94_CLK_HSIOPLL			41

#define IMX94_CLK_LDBPLL_VCO			42

#define IMX94_CLK_LDBPLL			43

#define IMX94_CLK_EXT1				44

#define IMX94_CLK_EXT2				45

#define IMX94_CLK_ADC				46

#define IMX94_CLK_BUSAON			47

#define IMX94_CLK_CAN1				48

#define IMX94_CLK_GLITCHFILTER			49

#define IMX94_CLK_GPT1				50

#define IMX94_CLK_I3C1SLOW			51

#define IMX94_CLK_LPI2C1			52

#define IMX94_CLK_LPI2C2			53

#define IMX94_CLK_LPSPI1			54

#define IMX94_CLK_LPSPI2			55

#define IMX94_CLK_LPTMR1			56

#define IMX94_CLK_LPUART1			57

#define IMX94_CLK_LPUART2			58

#define IMX94_CLK_M33				59

#define IMX94_CLK_M33SYSTICK			60

#define IMX94_CLK_PDM				61

#define IMX94_CLK_SAI1				62

#define IMX94_CLK_TPM2				63

#define IMX94_CLK_A55				64

#define IMX94_CLK_A55MTRBUS			65

#define IMX94_CLK_A55PERIPH			66

#define IMX94_CLK_DRAMALT			67

#define IMX94_CLK_DRAMAPB			68

#define IMX94_CLK_DISPAPB			69

#define IMX94_CLK_DISPAXI			70

#define IMX94_CLK_DISPPIX			71

#define IMX94_CLK_HSIOACSCAN480M		72

#define IMX94_CLK_HSIOACSCAN80M			73

#define IMX94_CLK_HSIO				74

#define IMX94_CLK_HSIOPCIEAUX			75

#define IMX94_CLK_HSIOPCIETEST160M		76

#define IMX94_CLK_HSIOPCIETEST400M		77

#define IMX94_CLK_HSIOPCIETEST500M		78

#define IMX94_CLK_HSIOPCIETEST50M		79

#define IMX94_CLK_HSIOUSBTEST60M		80

#define IMX94_CLK_BUSM70			81

#define IMX94_CLK_M70				82

#define IMX94_CLK_M70SYSTICK			83

#define IMX94_CLK_BUSM71			84

#define IMX94_CLK_M71				85

#define IMX94_CLK_M71SYSTICK			86

#define IMX94_CLK_BUSNETCMIX			87

#define IMX94_CLK_ECAT				88

#define IMX94_CLK_ENET				89

#define IMX94_CLK_ENETPHYTEST200M		90

#define IMX94_CLK_ENETPHYTEST500M		91

#define IMX94_CLK_ENETPHYTEST667M		92

#define IMX94_CLK_ENETREF			93

#define IMX94_CLK_ENETTIMER1			94

#define IMX94_CLK_ENETTIMER2			95

#define IMX94_CLK_ENETTIMER3			96

#define IMX94_CLK_FLEXIO3			97

#define IMX94_CLK_FLEXIO4			98

#define IMX94_CLK_M33SYNC			99

#define IMX94_CLK_M33SYNCSYSTICK		100

#define IMX94_CLK_MAC0				101

#define IMX94_CLK_MAC1				102

#define IMX94_CLK_MAC2				103

#define IMX94_CLK_MAC3				104

#define IMX94_CLK_MAC4				105

#define IMX94_CLK_MAC5				106

#define IMX94_CLK_NOCAPB			107

#define IMX94_CLK_NOC				108

#define IMX94_CLK_NPUAPB			109

#define IMX94_CLK_NPU				110

#define IMX94_CLK_CCMCKO1			111

#define IMX94_CLK_CCMCKO2			112

#define IMX94_CLK_CCMCKO3			113

#define IMX94_CLK_CCMCKO4			114

#define IMX94_CLK_BISS				115

#define IMX94_CLK_BUSWAKEUP			116

#define IMX94_CLK_CAN2				117

#define IMX94_CLK_CAN3				118

#define IMX94_CLK_CAN4				119

#define IMX94_CLK_CAN5				120

#define IMX94_CLK_ENDAT21			121

#define IMX94_CLK_ENDAT22			122

#define IMX94_CLK_ENDAT31FAST			123

#define IMX94_CLK_ENDAT31SLOW			124

#define IMX94_CLK_FLEXIO1			125

#define IMX94_CLK_FLEXIO2			126

#define IMX94_CLK_GPT2				127

#define IMX94_CLK_GPT3				128

#define IMX94_CLK_GPT4				129

#define IMX94_CLK_HIPERFACE1			130

#define IMX94_CLK_HIPERFACE1SYNC		131

#define IMX94_CLK_HIPERFACE2			132

#define IMX94_CLK_HIPERFACE2SYNC		133

#define IMX94_CLK_I3C2SLOW			134

#define IMX94_CLK_LPI2C3			135

#define IMX94_CLK_LPI2C4			136

#define IMX94_CLK_LPI2C5			137

#define IMX94_CLK_LPI2C6			138

#define IMX94_CLK_LPI2C7			139

#define IMX94_CLK_LPI2C8			140

#define IMX94_CLK_LPSPI3			141

#define IMX94_CLK_LPSPI4			142

#define IMX94_CLK_LPSPI5			143

#define IMX94_CLK_LPSPI6			144

#define IMX94_CLK_LPSPI7			145

#define IMX94_CLK_LPSPI8			146

#define IMX94_CLK_LPTMR2			147

#define IMX94_CLK_LPUART10			148

#define IMX94_CLK_LPUART11			149

#define IMX94_CLK_LPUART12			150

#define IMX94_CLK_LPUART3			151

#define IMX94_CLK_LPUART4			152

#define IMX94_CLK_LPUART5			153

#define IMX94_CLK_LPUART6			154

#define IMX94_CLK_LPUART7			155

#define IMX94_CLK_LPUART8			156

#define IMX94_CLK_LPUART9			157

#define IMX94_CLK_SAI2				158

#define IMX94_CLK_SAI3				159

#define IMX94_CLK_SAI4				160

#define IMX94_CLK_SWOTRACE			161

#define IMX94_CLK_TPM4				162

#define IMX94_CLK_TPM5				163

#define IMX94_CLK_TPM6				164

#define IMX94_CLK_USBPHYBURUNIN			165

#define IMX94_CLK_USDHC1			166

#define IMX94_CLK_USDHC2			167

#define IMX94_CLK_USDHC3			168

#define IMX94_CLK_V2XPK				169

#define IMX94_CLK_WAKEUPAXI			170

#define IMX94_CLK_XSPISLVROOT			171

#define IMX94_CLK_XSPI1				172

#define IMX94_CLK_XSPI2				173

#define IMX94_CLK_SEL_EXT			174

#define IMX94_CLK_SEL_A55C0			175

#define IMX94_CLK_SEL_A55C1			176

#define IMX94_CLK_SEL_A55C2			177

#define IMX94_CLK_SEL_A55C3			178

#define IMX94_CLK_SEL_A55P			179

#define IMX94_CLK_SEL_DRAM			180

#define IMX94_CLK_SEL_TEMPSENSE			181

#define IMX94_CLK_NPU_CGC			182



#endif /* __IMX94_CLOCK_H */

arch/arm64/boot/dts/freescale/imx94-pinfunc.h

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arch/arm64/boot/dts/freescale/imx94-power.h

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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */

/*

 *  Copyright 2024-2025 NXP

 */



#ifndef __IMX94_POWER_H

#define __IMX94_POWER_H



#define IMX94_PD_ANA		0

#define IMX94_PD_AON		1

#define IMX94_PD_BBSM		2

#define IMX94_PD_M71		3

#define IMX94_PD_CCMSRCGPC	4

#define IMX94_PD_A55C0		5

#define IMX94_PD_A55C1		6

#define IMX94_PD_A55C2		7

#define IMX94_PD_A55C3		8

#define IMX94_PD_A55P		9

#define IMX94_PD_DDR		10

#define IMX94_PD_DISPLAY	11

#define IMX94_PD_M70		12

#define IMX94_PD_HSIO_TOP	13

#define IMX94_PD_HSIO_WAON	14

#define IMX94_PD_NETC		15

#define IMX94_PD_NOC		16

#define IMX94_PD_NPU		17

#define IMX94_PD_WAKEUP		18



#define IMX94_PERF_M33		0

#define IMX94_PERF_M33S		1

#define IMX94_PERF_WAKEUP	2

#define IMX94_PERF_M70		3

#define IMX94_PERF_M71		4

#define IMX94_PERF_DRAM		5

#define IMX94_PERF_HSIO		6

#define IMX94_PERF_NPU		7

#define IMX94_PERF_NOC		8

#define IMX94_PERF_A55		9

#define IMX94_PERF_DISP		10



#endif /* __IMX94_POWER_H */

arch/arm64/boot/dts/freescale/imx94.dtsi

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arch/arm64/boot/dts/freescale/imx943.dtsi

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*

 * Copyright 2025 NXP

 */



#include "imx94.dtsi"



/ {

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		idle-states {

			entry-method = "psci";



			cpu_pd_wait: cpu-pd-wait {

				compatible = "arm,idle-state";

				arm,psci-suspend-param = <0x0010033>;

				local-timer-stop;

				entry-latency-us = <1000>;

				exit-latency-us = <700>;

				min-residency-us = <2700>;

				wakeup-latency-us = <1500>;

			};

		};



		cpu0: cpu@0 {

			compatible = "arm,cortex-a55";

			device_type = "cpu";

			reg = <0x0>;

			enable-method = "psci";

			#cooling-cells = <2>;

			cpu-idle-states = <&cpu_pd_wait>;

			power-domains = <&scmi_perf IMX94_PERF_A55>;

			power-domain-names = "perf";

			i-cache-size = <32768>;

			i-cache-line-size = <64>;

			i-cache-sets = <128>;

			d-cache-size = <32768>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&l2_cache_l0>;

		};



		cpu1: cpu@100 {

			compatible = "arm,cortex-a55";

			device_type = "cpu";

			reg = <0x100>;

			enable-method = "psci";

			#cooling-cells = <2>;

			cpu-idle-states = <&cpu_pd_wait>;

			power-domains = <&scmi_perf IMX94_PERF_A55>;

			power-domain-names = "perf";

			i-cache-size = <32768>;

			i-cache-line-size = <64>;

			i-cache-sets = <128>;

			d-cache-size = <32768>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&l2_cache_l1>;

		};



		cpu2: cpu@200 {

			compatible = "arm,cortex-a55";

			device_type = "cpu";

			reg = <0x200>;

			enable-method = "psci";

			#cooling-cells = <2>;

			cpu-idle-states = <&cpu_pd_wait>;

			power-domains = <&scmi_perf IMX94_PERF_A55>;

			power-domain-names = "perf";

			i-cache-size = <32768>;

			i-cache-line-size = <64>;

			i-cache-sets = <128>;

			d-cache-size = <32768>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&l2_cache_l2>;

		};



		cpu3: cpu@300 {

			compatible = "arm,cortex-a55";

			device_type = "cpu";

			reg = <0x300>;

			enable-method = "psci";

			#cooling-cells = <2>;

			cpu-idle-states = <&cpu_pd_wait>;

			power-domains = <&scmi_perf IMX94_PERF_A55>;

			power-domain-names = "perf";

			i-cache-size = <32768>;

			i-cache-line-size = <64>;

			i-cache-sets = <128>;

			d-cache-size = <32768>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&l2_cache_l3>;

		};



		l2_cache_l0: l2-cache-l0 {

			compatible = "cache";

			cache-size = <65536>;

			cache-line-size = <64>;

			cache-sets = <256>;

			cache-level = <2>;

			cache-unified;

			next-level-cache = <&l3_cache>;

		};



		l2_cache_l1: l2-cache-l1 {

			compatible = "cache";

			cache-size = <65536>;

			cache-line-size = <64>;

			cache-sets = <256>;

			cache-level = <2>;

			cache-unified;

			next-level-cache = <&l3_cache>;

		};



		l2_cache_l2: l2-cache-l2 {

			compatible = "cache";

			cache-size = <65536>;

			cache-line-size = <64>;

			cache-sets = <256>;

			cache-level = <2>;

			cache-unified;

			next-level-cache = <&l3_cache>;

		};



		l2_cache_l3: l2-cache-l3 {

			compatible = "cache";

			cache-size = <65536>;

			cache-line-size = <64>;

			cache-sets = <256>;

			cache-level = <2>;

			cache-unified;

			next-level-cache = <&l3_cache>;

		};



		l3_cache: l3-cache {

			compatible = "cache";

			cache-size = <1048576>;

			cache-line-size = <64>;

			cache-sets = <1024>;

			cache-level = <3>;

			cache-unified;

		};

	};

};