Commit b1089e0c authored by Dhananjay Ugwekar's avatar Dhananjay Ugwekar Committed by Mario Limonciello
Browse files

cpufreq/amd-pstate: Refactor amd_pstate_epp_reenable() and amd_pstate_epp_offline() 



Replace similar code chunks with amd_pstate_update_perf() and
amd_pstate_set_epp() function calls.

Signed-off-by: default avatarDhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
Reviewed-by: default avatarMario Limonciello <mario.limonciello@amd.com>
Reviewed-by: default avatarGautham R. Shenoy <gautham.shenoy@amd.com>
Link: https://lore.kernel.org/r/20241204144842.164178-4-Dhananjay.Ugwekar@amd.com


[ML: Fix LKP reported error about unused variable]
Signed-off-by: default avatarMario Limonciello <mario.limonciello@amd.com>
parent 57a2b25e

drivers/cpufreq/amd-pstate.c

+7 −31
Original line number Diff line number Diff line
@@ -1632,25 +1632,17 @@ static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy) 


static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata)

{

	struct cppc_perf_ctrls perf_ctrls;

	u64 value, max_perf;

	u64 max_perf;

	int ret;



	ret = amd_pstate_cppc_enable(true);

	if (ret)

		pr_err("failed to enable amd pstate during resume, return %d\n", ret);



	value = READ_ONCE(cpudata->cppc_req_cached);

	max_perf = READ_ONCE(cpudata->highest_perf);



	if (cpu_feature_enabled(X86_FEATURE_CPPC)) {

		wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);

	} else {

		perf_ctrls.max_perf = max_perf;

		cppc_set_perf(cpudata->cpu, &perf_ctrls);

		perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(cpudata->epp_cached);

		cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1);

	}

	amd_pstate_update_perf(cpudata, 0, 0, max_perf, false);

	amd_pstate_set_epp(cpudata, cpudata->epp_cached);

}



static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy)
@@ -1670,31 +1662,15 @@ static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy) 
static void amd_pstate_epp_offline(struct cpufreq_policy *policy)

{

	struct amd_cpudata *cpudata = policy->driver_data;

	struct cppc_perf_ctrls perf_ctrls;

	int min_perf;

	u64 value;



	min_perf = READ_ONCE(cpudata->lowest_perf);

	value = READ_ONCE(cpudata->cppc_req_cached);



	mutex_lock(&amd_pstate_limits_lock);

	if (cpu_feature_enabled(X86_FEATURE_CPPC)) {

		cpudata->epp_policy = CPUFREQ_POLICY_UNKNOWN;



		/* Set max perf same as min perf */

		value &= ~AMD_CPPC_MAX_PERF(~0L);

		value |= AMD_CPPC_MAX_PERF(min_perf);

		value &= ~AMD_CPPC_MIN_PERF(~0L);

		value |= AMD_CPPC_MIN_PERF(min_perf);

		wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);

	} else {

		perf_ctrls.desired_perf = 0;

		perf_ctrls.min_perf = min_perf;

		perf_ctrls.max_perf = min_perf;

		cppc_set_perf(cpudata->cpu, &perf_ctrls);

		perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(HWP_EPP_BALANCE_POWERSAVE);

		cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1);

	}

	amd_pstate_update_perf(cpudata, min_perf, 0, min_perf, false);

	amd_pstate_set_epp(cpudata, AMD_CPPC_EPP_BALANCE_POWERSAVE);



	mutex_unlock(&amd_pstate_limits_lock);

}