Commit b13cfb44 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2024-02-07' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



drm/i915 feature pull for v6.9:

Features and functionality:
- Early transport for panel replay and PSR (Jouni)
- New ARL PCI IDs (Matt)
- DP TPS4 PHY test pattern support (Khaled)

Refactoring and cleanups:
- Unify and improve VSC SDP for PSR and non-PSR cases (Jouni)
- Refactor memory regions and improve debug logging (Ville)
- Rework global state serialization (Ville)
- Remove unused CDCLK divider fields (Gustavo)
- Unify HDCP connector logging format (Jani)
- Use display instead of graphics version in display code (Jani)
- Move VBT and opregion debugfs next to the implementation (Jani)
- Abstract opregion interface, use opaque type (Jani)

Fixes:
- Fix MTL stolen memory access (Ville)
- Fix initial display plane readout for MTL (Ville)
- Fix HPD handling during driver init/shutdown (Imre)
- Cursor vblank evasion fixes (Ville)
- Various VSC SDP fixes (Jouni)
- Allow PSR mode changes without full modeset (Jouni)
- Fix CDCLK sanitization on module load for Xe2_LPD (Gustavo)
- Fix the max DSC bpc supported by the source (Ankit)
- Add missing LNL ALPM AUX wake configuration (Jouni)
- Cx0 PHY state readout and verify fixes (Mika)
- Fix PSR (panel replay) debugfs for MST connectors (Imre)
- Fail HDCP repeater authentication if Type1 device not present (Suraj)
- Ratelimit debug logging in vm_fault_ttm (Nirmoy)
- Use a fake PCH for MTL because south display is not on the PCH (Haridhar)
- Disable DSB for Xe driver for now (José)
- Fix some LNL display register changes (Lucas)
- Fix build on ChromeOS (Paz Zcharya)
- Preserve current shared DPLL for fastsets on Type-C ports (Ville)
- Fix state checker warnings for MG/TC/TBT PLLs (Ville)
- Fix HDCP repeater ctl register value on errors (Jani)
- Allow FBC with CCS modifiers on SKL+ (Ville)
- Fix HDCP GGTT pinning (Ville)

DRM core changes:
- Add ratelimited drm dbg print (Nirmoy)
- DPCD PSR early transport macro (Jouni)

Merges:
- Backmerge drm-next to bring Xe driver to drm-intel-next (Jani)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87cyt8cxsh.fsf@intel.com
parents b344e64f 449c2d59

drivers/gpu/drm/i915/display/i9xx_plane.c

+30 −0
Original line number Diff line number Diff line
@@ -1060,3 +1060,33 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, 


	plane_config->fb = intel_fb;

}



bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc,

				     const struct intel_initial_plane_config *plane_config)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	struct intel_plane *plane = to_intel_plane(crtc->base.primary);

	const struct intel_plane_state *plane_state =

		to_intel_plane_state(plane->base.state);

	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

	u32 base;



	if (!plane_state->uapi.visible)

		return false;



	base = intel_plane_ggtt_offset(plane_state);



	/*

	 * We may have moved the surface to a different

	 * part of ggtt, make the plane aware of that.

	 */

	if (plane_config->base == base)

		return false;



	if (DISPLAY_VER(dev_priv) >= 4)

		intel_de_write(dev_priv, DSPSURF(i9xx_plane), base);

	else

		intel_de_write(dev_priv, DSPADDR(i9xx_plane), base);



	return true;

}

drivers/gpu/drm/i915/display/i9xx_plane.h

+7 −0
Original line number Diff line number Diff line
@@ -26,6 +26,8 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe); 


void i9xx_get_initial_plane_config(struct intel_crtc *crtc,

				   struct intel_initial_plane_config *plane_config);

bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc,

				     const struct intel_initial_plane_config *plane_config);

#else

static inline unsigned int i965_plane_max_stride(struct intel_plane *plane,

						 u32 pixel_format, u64 modifier,
@@ -46,6 +48,11 @@ static inline void i9xx_get_initial_plane_config(struct intel_crtc *crtc, 
						 struct intel_initial_plane_config *plane_config)

{

}

static inline bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc,

						   const struct intel_initial_plane_config *plane_config)

{

	return false;

}

#endif



#endif

drivers/gpu/drm/i915/display/intel_atomic_plane.c

+3 −3
Original line number Diff line number Diff line
@@ -217,6 +217,9 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state, 
	int width, height;

	unsigned int rel_data_rate;



	if (plane->id == PLANE_CURSOR)

		return 0;



	if (!plane_state->uapi.visible)

		return 0;
@@ -244,9 +247,6 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state, 


	rel_data_rate = width * height * fb->format->cpp[color_plane];



	if (plane->id == PLANE_CURSOR)

		return rel_data_rate;



	return intel_adjusted_rate(&plane_state->uapi.src,

				   &plane_state->uapi.dst,

				   rel_data_rate);

drivers/gpu/drm/i915/display/intel_backlight.c

+1 −1
Original line number Diff line number Diff line
@@ -1465,7 +1465,7 @@ static bool cnp_backlight_controller_is_valid(struct drm_i915_private *i915, int 


	if (controller == 1 &&

	    INTEL_PCH_TYPE(i915) >= PCH_ICP &&

	    INTEL_PCH_TYPE(i915) < PCH_MTP)

	    INTEL_PCH_TYPE(i915) <= PCH_ADP)

		return intel_de_read(i915, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT;



	return true;

drivers/gpu/drm/i915/display/intel_bios.c

+32 −4
Original line number Diff line number Diff line
@@ -2204,8 +2204,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin) 
	if (IS_DGFX(i915))

		return vbt_pin;



	if (INTEL_PCH_TYPE(i915) >= PCH_LNL || HAS_PCH_MTP(i915) ||

	    IS_ALDERLAKE_P(i915)) {

	if (INTEL_PCH_TYPE(i915) >= PCH_MTL || IS_ALDERLAKE_P(i915)) {

		ddc_pin_map = adlp_ddc_pin_map;

		n_entries = ARRAY_SIZE(adlp_ddc_pin_map);

	} else if (IS_ALDERLAKE_S(i915)) {
@@ -3074,7 +3073,7 @@ static struct vbt_header *oprom_get_vbt(struct drm_i915_private *i915) 
 */

void intel_bios_init(struct drm_i915_private *i915)

{

	const struct vbt_header *vbt = i915->display.opregion.vbt;

	const struct vbt_header *vbt;

	struct vbt_header *oprom_vbt = NULL;

	const struct bdb_header *bdb;
@@ -3089,6 +3088,8 @@ void intel_bios_init(struct drm_i915_private *i915) 


	init_vbt_defaults(i915);



	vbt = intel_opregion_get_vbt(i915, NULL);



	/*

	 * If the OpRegion does not have VBT, look in SPI flash through MMIO or

	 * PCI mapping
@@ -3306,7 +3307,7 @@ bool intel_bios_is_lvds_present(struct drm_i915_private *i915, u8 *i2c_pin) 
		 * additional data.  Trust that if the VBT was written into

		 * the OpRegion then they have validated the LVDS's existence.

		 */

		if (i915->display.opregion.vbt)

		if (intel_opregion_get_vbt(i915, NULL))

			return true;

	}
@@ -3657,3 +3658,30 @@ void intel_bios_for_each_encoder(struct drm_i915_private *i915, 
	list_for_each_entry(devdata, &i915->display.vbt.display_devices, node)

		func(i915, devdata);

}



static int intel_bios_vbt_show(struct seq_file *m, void *unused)

{

	struct drm_i915_private *i915 = m->private;

	const void *vbt;

	size_t vbt_size;



	/*

	 * FIXME: VBT might originate from other places than opregion, and then

	 * this would be incorrect.

	 */

	vbt = intel_opregion_get_vbt(i915, &vbt_size);

	if (vbt)

		seq_write(m, vbt, vbt_size);



	return 0;

}



DEFINE_SHOW_ATTRIBUTE(intel_bios_vbt);



void intel_bios_debugfs_register(struct drm_i915_private *i915)

{

	struct drm_minor *minor = i915->drm.primary;



	debugfs_create_file("i915_vbt", 0444, minor->debugfs_root,

			    i915, &intel_bios_vbt_fops);

}