Unverified Commit b176dab2 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'qcom-clk-for-6.16' of... 

Merge tag 'qcom-clk-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Pull Qualcomm clk driver updates from Bjorn Andersson:

 - Camera clock controller driver for Qualcomm QCS8300
 - Correct wait_val values for a variety of Qualcomm GDSCs
 - Fix Qualcomm X Elite UFS clock settings
 - Allow clkaN to be optional in the Qualcomm RPMh clock controller
   driver if command db doesn't define it
parents 0af2f6be 201bf08b

Documentation/devicetree/bindings/clock/qcom,videocc.yaml

+20 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ description: | 
  domains on Qualcomm SoCs.



  See also::

    include/dt-bindings/clock/qcom,sm6350-videocc.h

    include/dt-bindings/clock/qcom,videocc-sc7180.h

    include/dt-bindings/clock/qcom,videocc-sc7280.h

    include/dt-bindings/clock/qcom,videocc-sdm845.h
@@ -26,6 +27,7 @@ properties: 
      - qcom,sc7180-videocc

      - qcom,sc7280-videocc

      - qcom,sdm845-videocc

      - qcom,sm6350-videocc

      - qcom,sm8150-videocc

      - qcom,sm8250-videocc
@@ -87,6 +89,24 @@ allOf: 
            - const: bi_tcxo

            - const: bi_tcxo_ao



  - if:

      properties:

        compatible:

          enum:

            - qcom,sm6350-videocc

    then:

      properties:

        clocks:

          items:

            - description: Video AHB clock from GCC

            - description: Board XO source

            - description: Sleep Clock source

        clock-names:

          items:

            - const: iface

            - const: bi_tcxo

            - const: sleep_clk



  - if:

      properties:

        compatible:

drivers/clk/qcom/apcs-sdx55.c

+5 −1
Original line number Diff line number Diff line
@@ -111,7 +111,11 @@ static int qcom_apcs_sdx55_clk_probe(struct platform_device *pdev) 
	 * driver, there seems to be no better place to do this. So do it here!

	 */

	cpu_dev = get_cpu_device(0);

	dev_pm_domain_attach(cpu_dev, true);

	ret = dev_pm_domain_attach(cpu_dev, true);

	if (ret) {

		dev_err_probe(dev, ret, "can't get PM domain: %d\n", ret);

		goto err;

	}



	return 0;

drivers/clk/qcom/camcc-sa8775p.c

+98 −5
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ 
#include <linux/pm_runtime.h>

#include <linux/regmap.h>



#include <dt-bindings/clock/qcom,sa8775p-camcc.h>

#include <dt-bindings/clock/qcom,qcs8300-camcc.h>



#include "clk-alpha-pll.h"

#include "clk-branch.h"
@@ -1681,6 +1681,24 @@ static struct clk_branch cam_cc_sm_obs_clk = { 
	},

};



static struct clk_branch cam_cc_titan_top_accu_shift_clk = {

	.halt_reg = 0x131f0,

	.halt_check = BRANCH_HALT_VOTED,

	.clkr = {

		.enable_reg = 0x131f0,

		.enable_mask = BIT(0),

		.hw.init = &(const struct clk_init_data) {

			.name = "cam_cc_titan_top_accu_shift_clk",

			.parent_hws = (const struct clk_hw*[]) {

				&cam_cc_xo_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct gdsc cam_cc_titan_top_gdsc = {

	.gdscr = 0x131bc,

	.en_rest_wait_val = 0x2,
@@ -1775,6 +1793,7 @@ static struct clk_regmap *cam_cc_sa8775p_clocks[] = { 
	[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,

	[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,

	[CAM_CC_SM_OBS_CLK] = &cam_cc_sm_obs_clk.clkr,

	[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] = NULL,

	[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,

	[CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,

};
@@ -1811,6 +1830,7 @@ static const struct qcom_cc_desc cam_cc_sa8775p_desc = { 
};



static const struct of_device_id cam_cc_sa8775p_match_table[] = {

	{ .compatible = "qcom,qcs8300-camcc" },

	{ .compatible = "qcom,sa8775p-camcc" },

	{ }

};
@@ -1841,10 +1861,83 @@ static int cam_cc_sa8775p_probe(struct platform_device *pdev) 
	clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);

	clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);



	if (device_is_compatible(&pdev->dev, "qcom,qcs8300-camcc")) {

		cam_cc_camnoc_axi_clk_src.cmd_rcgr = 0x13154;

		cam_cc_camnoc_axi_clk.halt_reg = 0x1316c;

		cam_cc_camnoc_axi_clk.clkr.enable_reg = 0x1316c;

		cam_cc_camnoc_dcd_xo_clk.halt_reg = 0x13174;

		cam_cc_camnoc_dcd_xo_clk.clkr.enable_reg = 0x13174;



		cam_cc_csi0phytimer_clk_src.cmd_rcgr = 0x15054;

		cam_cc_csi1phytimer_clk_src.cmd_rcgr = 0x15078;

		cam_cc_csi2phytimer_clk_src.cmd_rcgr = 0x15098;

		cam_cc_csid_clk_src.cmd_rcgr = 0x13134;



		cam_cc_mclk0_clk_src.cmd_rcgr = 0x15000;

		cam_cc_mclk1_clk_src.cmd_rcgr = 0x1501c;

		cam_cc_mclk2_clk_src.cmd_rcgr = 0x15038;



		cam_cc_fast_ahb_clk_src.cmd_rcgr = 0x13104;

		cam_cc_slow_ahb_clk_src.cmd_rcgr = 0x1311c;

		cam_cc_xo_clk_src.cmd_rcgr = 0x131b8;

		cam_cc_sleep_clk_src.cmd_rcgr = 0x131d4;



		cam_cc_core_ahb_clk.halt_reg = 0x131b4;

		cam_cc_core_ahb_clk.clkr.enable_reg = 0x131b4;



		cam_cc_cpas_ahb_clk.halt_reg = 0x130f4;

		cam_cc_cpas_ahb_clk.clkr.enable_reg = 0x130f4;

		cam_cc_cpas_fast_ahb_clk.halt_reg = 0x130fc;

		cam_cc_cpas_fast_ahb_clk.clkr.enable_reg = 0x130fc;



		cam_cc_csi0phytimer_clk.halt_reg = 0x1506c;

		cam_cc_csi0phytimer_clk.clkr.enable_reg = 0x1506c;

		cam_cc_csi1phytimer_clk.halt_reg = 0x15090;

		cam_cc_csi1phytimer_clk.clkr.enable_reg = 0x15090;

		cam_cc_csi2phytimer_clk.halt_reg = 0x150b0;

		cam_cc_csi2phytimer_clk.clkr.enable_reg = 0x150b0;

		cam_cc_csid_clk.halt_reg = 0x1314c;

		cam_cc_csid_clk.clkr.enable_reg = 0x1314c;

		cam_cc_csid_csiphy_rx_clk.halt_reg = 0x15074;

		cam_cc_csid_csiphy_rx_clk.clkr.enable_reg = 0x15074;

		cam_cc_csiphy0_clk.halt_reg = 0x15070;

		cam_cc_csiphy0_clk.clkr.enable_reg = 0x15070;

		cam_cc_csiphy1_clk.halt_reg = 0x15094;

		cam_cc_csiphy1_clk.clkr.enable_reg = 0x15094;

		cam_cc_csiphy2_clk.halt_reg = 0x150b4;

		cam_cc_csiphy2_clk.clkr.enable_reg = 0x150b4;



		cam_cc_mclk0_clk.halt_reg = 0x15018;

		cam_cc_mclk0_clk.clkr.enable_reg = 0x15018;

		cam_cc_mclk1_clk.halt_reg = 0x15034;

		cam_cc_mclk1_clk.clkr.enable_reg = 0x15034;

		cam_cc_mclk2_clk.halt_reg = 0x15050;

		cam_cc_mclk2_clk.clkr.enable_reg = 0x15050;

		cam_cc_qdss_debug_xo_clk.halt_reg = 0x1319c;

		cam_cc_qdss_debug_xo_clk.clkr.enable_reg = 0x1319c;



		cam_cc_titan_top_gdsc.gdscr = 0x131a0;



		cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK] = NULL;

		cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK_SRC] = NULL;

		cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK] = NULL;

		cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK_SRC] = NULL;

		cam_cc_sa8775p_clocks[CAM_CC_CSIPHY3_CLK] = NULL;

		cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK] = NULL;

		cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK_SRC] = NULL;

		cam_cc_sa8775p_clocks[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] =

				&cam_cc_titan_top_accu_shift_clk.clkr;



		/* Keep some clocks always enabled */

		qcom_branch_set_clk_en(regmap, 0x13178); /* CAM_CC_CAMNOC_XO_CLK */

		qcom_branch_set_clk_en(regmap, 0x131d0); /* CAM_CC_GDSC_CLK */

		qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_SLEEP_CLK */

	} else {

		/* Keep some clocks always enabled */

		qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */

		qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */

		qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */

	}



	ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sa8775p_desc, regmap);

drivers/clk/qcom/camcc-sm6350.c

+18 −0
Original line number Diff line number Diff line
@@ -1695,6 +1695,9 @@ static struct clk_branch camcc_sys_tmr_clk = { 


static struct gdsc bps_gdsc = {

	.gdscr = 0x6004,

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "bps_gdsc",

	},
@@ -1704,6 +1707,9 @@ static struct gdsc bps_gdsc = { 


static struct gdsc ipe_0_gdsc = {

	.gdscr = 0x7004,

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "ipe_0_gdsc",

	},
@@ -1713,6 +1719,9 @@ static struct gdsc ipe_0_gdsc = { 


static struct gdsc ife_0_gdsc = {

	.gdscr = 0x9004,

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "ife_0_gdsc",

	},
@@ -1721,6 +1730,9 @@ static struct gdsc ife_0_gdsc = { 


static struct gdsc ife_1_gdsc = {

	.gdscr = 0xa004,

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "ife_1_gdsc",

	},
@@ -1729,6 +1741,9 @@ static struct gdsc ife_1_gdsc = { 


static struct gdsc ife_2_gdsc = {

	.gdscr = 0xb004,

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "ife_2_gdsc",

	},
@@ -1737,6 +1752,9 @@ static struct gdsc ife_2_gdsc = { 


static struct gdsc titan_top_gdsc = {

	.gdscr = 0x14004,

	.en_rest_wait_val = 0x2,

	.en_few_wait_val = 0x2,

	.clk_dis_wait_val = 0xf,

	.pd = {

		.name = "titan_top_gdsc",

	},

drivers/clk/qcom/clk-rpmh.c

+11 −0
Original line number Diff line number Diff line
@@ -66,6 +66,8 @@ struct clk_rpmh { 
struct clk_rpmh_desc {

	struct clk_hw **clks;

	size_t num_clks;

	/* RPMh clock clkaN are optional for this platform */

	bool clka_optional;

};



static DEFINE_MUTEX(rpmh_clk_lock);
@@ -648,6 +650,7 @@ static struct clk_hw *sm8550_rpmh_clocks[] = { 
static const struct clk_rpmh_desc clk_rpmh_sm8550 = {

	.clks = sm8550_rpmh_clocks,

	.num_clks = ARRAY_SIZE(sm8550_rpmh_clocks),

	.clka_optional = true,

};



static struct clk_hw *sm8650_rpmh_clocks[] = {
@@ -679,6 +682,7 @@ static struct clk_hw *sm8650_rpmh_clocks[] = { 
static const struct clk_rpmh_desc clk_rpmh_sm8650 = {

	.clks = sm8650_rpmh_clocks,

	.num_clks = ARRAY_SIZE(sm8650_rpmh_clocks),

	.clka_optional = true,

};



static struct clk_hw *sc7280_rpmh_clocks[] = {
@@ -847,6 +851,7 @@ static struct clk_hw *sm8750_rpmh_clocks[] = { 
static const struct clk_rpmh_desc clk_rpmh_sm8750 = {

	.clks = sm8750_rpmh_clocks,

	.num_clks = ARRAY_SIZE(sm8750_rpmh_clocks),

	.clka_optional = true,

};



static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
@@ -890,6 +895,12 @@ static int clk_rpmh_probe(struct platform_device *pdev) 
		rpmh_clk = to_clk_rpmh(hw_clks[i]);

		res_addr = cmd_db_read_addr(rpmh_clk->res_name);

		if (!res_addr) {

			hw_clks[i] = NULL;



			if (desc->clka_optional &&

			    !strncmp(rpmh_clk->res_name, "clka", sizeof("clka") - 1))

				continue;



			dev_err(&pdev->dev, "missing RPMh resource address for %s\n",

				rpmh_clk->res_name);

			return -ENODEV;