Commit b190eaea authored by Taniya Das's avatar Taniya Das Committed by Bjorn Andersson
Browse files

dt-bindings: clock: qcom: Add SM8750 video clock controller 



Add compatible string for SM8750 video clock controller and the bindings
for SM8750 Qualcomm SoC.

Signed-off-by: default avatarTaniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20251118-sm8750-videocc-v2-v4-4-049882a70c9f@oss.qualcomm.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent aa788d3b

Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml

+4 −1
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: Qualcomm Video Clock & Reset Controller on SM8450



maintainers:

  - Taniya Das <quic_tdas@quicinc.com>

  - Taniya Das <taniya.das@oss.qualcomm.com>

  - Jagadeesh Kona <quic_jkona@quicinc.com>



description: |
@@ -17,6 +17,7 @@ description: | 
  See also:

    include/dt-bindings/clock/qcom,sm8450-videocc.h

    include/dt-bindings/clock/qcom,sm8650-videocc.h

    include/dt-bindings/clock/qcom,sm8750-videocc.h



properties:

  compatible:
@@ -25,6 +26,7 @@ properties: 
      - qcom,sm8475-videocc

      - qcom,sm8550-videocc

      - qcom,sm8650-videocc

      - qcom,sm8750-videocc

      - qcom,x1e80100-videocc



  clocks:
@@ -61,6 +63,7 @@ allOf: 
            enum:

              - qcom,sm8450-videocc

              - qcom,sm8550-videocc

              - qcom,sm8750-videocc

    then:

      required:

        - required-opps

include/dt-bindings/clock/qcom,sm8750-videocc.h

0 → 100644
+40 −0
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

/*

 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8750_H

#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8750_H



/* VIDEO_CC clocks */

#define VIDEO_CC_AHB_CLK					0

#define VIDEO_CC_AHB_CLK_SRC					1

#define VIDEO_CC_MVS0_CLK					2

#define VIDEO_CC_MVS0_CLK_SRC					3

#define VIDEO_CC_MVS0_DIV_CLK_SRC				4

#define VIDEO_CC_MVS0_FREERUN_CLK				5

#define VIDEO_CC_MVS0_SHIFT_CLK					6

#define VIDEO_CC_MVS0C_CLK					7

#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC				8

#define VIDEO_CC_MVS0C_FREERUN_CLK				9

#define VIDEO_CC_MVS0C_SHIFT_CLK				10

#define VIDEO_CC_PLL0						11

#define VIDEO_CC_SLEEP_CLK					12

#define VIDEO_CC_SLEEP_CLK_SRC					13

#define VIDEO_CC_XO_CLK						14

#define VIDEO_CC_XO_CLK_SRC					15



/* VIDEO_CC power domains */

#define VIDEO_CC_MVS0_GDSC					0

#define VIDEO_CC_MVS0C_GDSC					1



/* VIDEO_CC resets */

#define VIDEO_CC_INTERFACE_BCR					0

#define VIDEO_CC_MVS0_BCR					1

#define VIDEO_CC_MVS0C_CLK_ARES					2

#define VIDEO_CC_MVS0C_BCR					3

#define VIDEO_CC_MVS0_FREERUN_CLK_ARES				4

#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES				5

#define VIDEO_CC_XO_CLK_ARES					6



#endif