Commit b1c1c524 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2025-09-05' of... 

Merge tag 'drm-intel-next-2025-09-05' of https://gitlab.freedesktop.org/drm/i915/kernel

 into drm-next

Cross-subsystem Changes:
 - iopoll: Generalize read_poll_timeout() into poll_timeout_us() (Ville)

Non-display related:
 - PREEMPT_RT fix (Sebastian)
 - Replace DRM_DEBUG_SELFTEST with DRM_KUNIT_TEST (Ruben, Imre)
 - Some changes oeveral like in RPS, SoC, debugfs targeting display separation (Jani)

Display related:
 - General refactor in favor of intel_display (Suraj)
 - Prune modes for YUV420 (Suraj)
 - Reject HBR3 in any eDP Panel (Ankit)
 - Change AUX DPCD probe address (Imre)
 - Display Wa fix, additions, and updates (Ankit, Vinod, Nemesa, Suraj, Jouni))
 - DP: Fix 2.7 Gbps link training on g4x (Ville)
 - DP: Adjust the idle pattern handling (Ville)
 - DP: Shuffle the link training code a bit (Ville)
 - Don't set/read the DSI C clock divider on GLK (Ville)
 - Precompute plane SURF address/etc (Ville)
 - Enable_psr kernel parameter changes (Jouni)
 - PHY LFPS sending configuration fixes (Jouni)
 - Fix dma_fence_wait_timeout() return value handling (Aakash)
 - DP: Fix disabling training pattern (Imre)
 - Small code clean-ups (Gustavo, Colin, Jani, Juha-Pekka)
 - Change vblank log from err to debug (Suraj)
 - More display clean-up towards intel_display split (Jani)
 - Use the recomended min_hblank values (Arun)
 - Block hpd during suspend (Dibin)
 - DSI: Fix overflow issue in pclk parsing (Jouni)
 - PSR: Do not trigger Frame Change events from frontbuffer flush (Jouni)
 - VBT cleanups and new fields (Jani, Suraj)
 - Type-C enabled/disconnected dp-alt sink (Imre)
 - Optimize panel power-on wait time (Dibin)
 - Wildcat Lake enabling (Imre, Chaitanya)
 - DP HDR updates (Chaitanya)
 - Fix divide by 0 error in i9xx_set_backlight (Suraj)
 - Fixes for PSR (Jouni)
 - Remove the encoder check in hdcp enable (Suraj)
 - Control HDMI output bpc (Lee)
 - Fix possible overflow on tc power (Mika)
 - Convert code towards poll_timeout_* (Jani)
 - Use REG_BIT on FW_BLC_SELF_* macros (Luca)
 - ALPM LFPS and silence period calculation (Jouni)
 - Remove power state verification before HW readout (Imre)
 - Fix HPD mtp_tc_hpd_enable_detection (Ville)
 - DRAM detection (Ville)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://lore.kernel.org/r/aLtc-gk3jhwcWxZh@intel.com
parents 6dc1d3c1 70a9b201

drivers/gpu/drm/i915/Kconfig.debug

+1 −1
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ config DRM_I915_DEBUG 
	select DRM_VGEM # used by igt/prime_vgem (dmabuf interop checks)

	select DRM_DEBUG_MM if DRM=y

	select DRM_EXPORT_FOR_TESTS if m

	select DRM_DEBUG_SELFTEST

	select DRM_KUNIT_TEST if KUNIT

	select DMABUF_SELFTESTS

	select SW_SYNC # signaling validation framework (igt/syncobj*)

	select DRM_I915_WERROR

drivers/gpu/drm/i915/display/g4x_dp.c

+32 −19
Original line number Diff line number Diff line
@@ -424,17 +424,6 @@ intel_dp_link_down(struct intel_encoder *encoder, 


	drm_dbg_kms(display->drm, "\n");



	if ((display->platform.ivybridge && port == PORT_A) ||

	    (HAS_PCH_CPT(display) && port != PORT_A)) {

		intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;

		intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;

	} else {

		intel_dp->DP &= ~DP_LINK_TRAIN_MASK;

		intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;

	}

	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(display, intel_dp->output_reg);



	intel_dp->DP &= ~DP_PORT_EN;

	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(display, intel_dp->output_reg);
@@ -611,6 +600,19 @@ cpt_set_link_train(struct intel_dp *intel_dp, 
	intel_de_posting_read(display, intel_dp->output_reg);

}



static void

cpt_set_idle_link_train(struct intel_dp *intel_dp,

			const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(intel_dp);



	intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;

	intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;



	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(display, intel_dp->output_reg);

}



static void

g4x_set_link_train(struct intel_dp *intel_dp,

		   const struct intel_crtc_state *crtc_state,
@@ -639,6 +641,19 @@ g4x_set_link_train(struct intel_dp *intel_dp, 
	intel_de_posting_read(display, intel_dp->output_reg);

}



static void

g4x_set_idle_link_train(struct intel_dp *intel_dp,

			const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(intel_dp);



	intel_dp->DP &= ~DP_LINK_TRAIN_MASK;

	intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;



	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(display, intel_dp->output_reg);

}



static void intel_dp_enable_port(struct intel_dp *intel_dp,

				 const struct intel_crtc_state *crtc_state)

{
@@ -1285,12 +1300,10 @@ bool g4x_dp_init(struct intel_display *display, 
		drm_dbg_kms(display->drm, "No VBT child device for DP-%c\n",

			    port_name(port));



	dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);

	dig_port = intel_dig_port_alloc();

	if (!dig_port)

		return false;



	dig_port->aux_ch = AUX_CH_NONE;



	intel_connector = intel_connector_alloc();

	if (!intel_connector)

		goto err_connector_alloc;
@@ -1300,8 +1313,6 @@ bool g4x_dp_init(struct intel_display *display, 


	intel_encoder->devdata = devdata;



	mutex_init(&dig_port->hdcp.mutex);



	if (drm_encoder_init(display->drm, &intel_encoder->base,

			     &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,

			     "DP %c", port_name(port)))
@@ -1342,10 +1353,13 @@ bool g4x_dp_init(struct intel_display *display, 
	intel_encoder->audio_disable = g4x_dp_audio_disable;



	if ((display->platform.ivybridge && port == PORT_A) ||

	    (HAS_PCH_CPT(display) && port != PORT_A))

	    (HAS_PCH_CPT(display) && port != PORT_A)) {

		dig_port->dp.set_link_train = cpt_set_link_train;

	else

		dig_port->dp.set_idle_link_train = cpt_set_idle_link_train;

	} else {

		dig_port->dp.set_link_train = g4x_set_link_train;

		dig_port->dp.set_idle_link_train = g4x_set_idle_link_train;

	}



	if (display->platform.cherryview)

		intel_encoder->set_signal_levels = chv_set_signal_levels;
@@ -1368,7 +1382,6 @@ bool g4x_dp_init(struct intel_display *display, 
	}



	dig_port->dp.output_reg = output_reg;

	dig_port->max_lanes = 4;



	intel_encoder->type = INTEL_OUTPUT_DP;

	intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port);

drivers/gpu/drm/i915/display/g4x_hdmi.c

+3 −12
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ 
#include "intel_display_types.h"

#include "intel_dp_aux.h"

#include "intel_dpio_phy.h"

#include "intel_fdi.h"

#include "intel_encoder.h"

#include "intel_fifo_underrun.h"

#include "intel_hdmi.h"

#include "intel_hotplug.h"
@@ -135,11 +135,8 @@ static int g4x_hdmi_compute_config(struct intel_encoder *encoder, 
	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);



	if (HAS_PCH_SPLIT(display)) {

	if (HAS_PCH_SPLIT(display))

		crtc_state->has_pch_encoder = true;

		if (!intel_fdi_compute_pipe_bpp(crtc_state))

			return -EINVAL;

	}



	if (display->platform.g4x)

		crtc_state->has_hdmi_sink = g4x_compute_has_hdmi_sink(state, crtc);
@@ -690,12 +687,10 @@ bool g4x_hdmi_init(struct intel_display *display, 
		drm_dbg_kms(display->drm, "No VBT child device for HDMI-%c\n",

			    port_name(port));



	dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);

	dig_port = intel_dig_port_alloc();

	if (!dig_port)

		return false;



	dig_port->aux_ch = AUX_CH_NONE;



	intel_connector = intel_connector_alloc();

	if (!intel_connector)

		goto err_connector_alloc;
@@ -704,8 +699,6 @@ bool g4x_hdmi_init(struct intel_display *display, 


	intel_encoder->devdata = devdata;



	mutex_init(&dig_port->hdcp.mutex);



	if (drm_encoder_init(display->drm, &intel_encoder->base,

			     &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,

			     "HDMI %c", port_name(port)))
@@ -767,8 +760,6 @@ bool g4x_hdmi_init(struct intel_display *display, 
		intel_encoder->cloneable |= BIT(INTEL_OUTPUT_HDMI);



	dig_port->hdmi.hdmi_reg = hdmi_reg;

	dig_port->dp.output_reg = INVALID_MMIO_REG;

	dig_port->max_lanes = 4;



	intel_infoframe_init(dig_port);

drivers/gpu/drm/i915/display/i9xx_plane.c

+29 −29
Original line number Diff line number Diff line
@@ -155,8 +155,7 @@ static bool i9xx_plane_has_windowing(struct intel_plane *plane) 
			i9xx_plane == PLANE_C;

}



static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,

			  const struct intel_plane_state *plane_state)

static u32 i9xx_plane_ctl(const struct intel_plane_state *plane_state)

{

	struct intel_display *display = to_intel_display(plane_state);

	const struct drm_framebuffer *fb = plane_state->hw.fb;
@@ -355,11 +354,24 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state, 
	if (ret)

		return ret;



	plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);

	plane_state->ctl = i9xx_plane_ctl(plane_state);



	return 0;

}



static u32 i8xx_plane_surf_offset(const struct intel_plane_state *plane_state)

{

	int x = plane_state->view.color_plane[0].x;

	int y = plane_state->view.color_plane[0].y;



	return intel_fb_xy_to_linear(x, y, plane_state, 0);

}



u32 i965_plane_surf_offset(const struct intel_plane_state *plane_state)

{

	return plane_state->view.color_plane[0].offset;

}



static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(crtc_state);
@@ -463,7 +475,7 @@ static void i9xx_plane_update_arm(struct intel_dsb *dsb, 
	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

	int x = plane_state->view.color_plane[0].x;

	int y = plane_state->view.color_plane[0].y;

	u32 dspcntr, dspaddr_offset, linear_offset;

	u32 dspcntr;



	dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
@@ -472,13 +484,6 @@ static void i9xx_plane_update_arm(struct intel_dsb *dsb, 
	    crtc_state->async_flip_planes & BIT(plane->id))

		dspcntr |= DISP_ASYNC_FLIP;



	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);



	if (DISPLAY_VER(display) >= 4)

		dspaddr_offset = plane_state->view.color_plane[0].offset;

	else

		dspaddr_offset = linear_offset;



	if (display->platform.cherryview && i9xx_plane == PLANE_B) {

		int crtc_x = plane_state->uapi.dst.x1;

		int crtc_y = plane_state->uapi.dst.y1;
@@ -498,7 +503,7 @@ static void i9xx_plane_update_arm(struct intel_dsb *dsb, 
				  DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));

	} else if (DISPLAY_VER(display) >= 4) {

		intel_de_write_fw(display, DSPLINOFF(display, i9xx_plane),

				  linear_offset);

				  intel_fb_xy_to_linear(x, y, plane_state, 0));

		intel_de_write_fw(display, DSPTILEOFF(display, i9xx_plane),

				  DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));

	}
@@ -511,11 +516,9 @@ static void i9xx_plane_update_arm(struct intel_dsb *dsb, 
	intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);



	if (DISPLAY_VER(display) >= 4)

		intel_de_write_fw(display, DSPSURF(display, i9xx_plane),

				  intel_plane_ggtt_offset(plane_state) + dspaddr_offset);

		intel_de_write_fw(display, DSPSURF(display, i9xx_plane), plane_state->surf);

	else

		intel_de_write_fw(display, DSPADDR(display, i9xx_plane),

				  intel_plane_ggtt_offset(plane_state) + dspaddr_offset);

		intel_de_write_fw(display, DSPADDR(display, i9xx_plane), plane_state->surf);

}



static void i830_plane_update_arm(struct intel_dsb *dsb,
@@ -604,16 +607,13 @@ g4x_primary_async_flip(struct intel_dsb *dsb, 
{

	struct intel_display *display = to_intel_display(plane);

	u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);

	u32 dspaddr_offset = plane_state->view.color_plane[0].offset;

	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;



	if (async_flip)

		dspcntr |= DISP_ASYNC_FLIP;



	intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr);



	intel_de_write_fw(display, DSPSURF(display, i9xx_plane),

			  intel_plane_ggtt_offset(plane_state) + dspaddr_offset);

	intel_de_write_fw(display, DSPSURF(display, i9xx_plane), plane_state->surf);

}



static void
@@ -624,11 +624,9 @@ vlv_primary_async_flip(struct intel_dsb *dsb, 
		       bool async_flip)

{

	struct intel_display *display = to_intel_display(plane);

	u32 dspaddr_offset = plane_state->view.color_plane[0].offset;

	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;



	intel_de_write_fw(display, DSPADDR_VLV(display, i9xx_plane),

			  intel_plane_ggtt_offset(plane_state) + dspaddr_offset);

	intel_de_write_fw(display, DSPADDR_VLV(display, i9xx_plane), plane_state->surf);

}



static void
@@ -1037,6 +1035,11 @@ intel_primary_plane_create(struct intel_display *display, enum pipe pipe) 
	plane->get_hw_state = i9xx_plane_get_hw_state;

	plane->check_plane = i9xx_plane_check;



	if (DISPLAY_VER(display) >= 4)

		plane->surf_offset = i965_plane_surf_offset;

	else

		plane->surf_offset = i8xx_plane_surf_offset;



	if (DISPLAY_VER(display) >= 5 || display->platform.g4x)

		plane->capture_error = g4x_primary_capture_error;

	else if (DISPLAY_VER(display) >= 4)
@@ -1254,24 +1257,21 @@ bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc, 
	const struct intel_plane_state *plane_state =

		to_intel_plane_state(plane->base.state);

	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

	u32 base;



	if (!plane_state->uapi.visible)

		return false;



	base = intel_plane_ggtt_offset(plane_state);



	/*

	 * We may have moved the surface to a different

	 * part of ggtt, make the plane aware of that.

	 */

	if (plane_config->base == base)

	if (plane_config->base == plane_state->surf)

		return false;



	if (DISPLAY_VER(display) >= 4)

		intel_de_write(display, DSPSURF(display, i9xx_plane), base);

		intel_de_write(display, DSPSURF(display, i9xx_plane), plane_state->surf);

	else

		intel_de_write(display, DSPADDR(display, i9xx_plane), base);

		intel_de_write(display, DSPADDR(display, i9xx_plane), plane_state->surf);



	return true;

}

drivers/gpu/drm/i915/display/i9xx_plane.h

+1 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ unsigned int vlv_plane_min_alignment(struct intel_plane *plane, 
				     const struct drm_framebuffer *fb,

				     int colot_plane);

int i9xx_check_plane_surface(struct intel_plane_state *plane_state);

u32 i965_plane_surf_offset(const struct intel_plane_state *plane_state);



struct intel_plane *

intel_primary_plane_create(struct intel_display *display, enum pipe pipe);