Commit b1f9ec65 authored by Siddharth Vadapalli's avatar Siddharth Vadapalli Committed by Nishanth Menon
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arm64: dts: ti: k3-j784s4-j742s2-main-common: Switch to 64-bit address space for PCIe0 and PCIe1 



The PCIe0 and PCIe1 instances of PCIe in J742S2 and J784S4 SoCs support:
1. 128 MB address region in the 32-bit address space
2. 4 GB address region in the 64-bit address space

The default configuration is that of a 128 MB address region in the
32-bit address space. While this might be sufficient for most use-cases,
it is insufficient for supporting use-cases which require larger address
spaces. Therefore, switch to using the 64-bit address space with a 4 GB
address region.

Signed-off-by: default avatarSiddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: default avatarUdit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20250422120042.3746004-8-s-vadapalli@ti.com


Signed-off-by: default avatarNishanth Menon <nm@ti.com>
parent 0fde0032

arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -1055,7 +1055,7 @@ pcie0_rc: pcie@2900000 { 
		reg = <0x00 0x02900000 0x00 0x1000>,

		      <0x00 0x02907000 0x00 0x400>,

		      <0x00 0x0d000000 0x00 0x00800000>,

		      <0x00 0x10000000 0x00 0x00001000>;

		      <0x40 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */

		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";

		interrupt-names = "link_state";

		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
@@ -1073,8 +1073,8 @@ pcie0_rc: pcie@2900000 { 
		device-id = <0xb012>;

		msi-map = <0x0 &gic_its 0x0 0x10000>;

		dma-coherent;

		ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,

			 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;

		ranges = <0x01000000 0x00 0x00001000 0x40 0x00001000 0x00 0x00100000>, /* IO (1 MB) */

			 <0x02000000 0x00 0x00101000 0x40 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */

		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;

		status = "disabled";

	};
@@ -1084,7 +1084,7 @@ pcie1_rc: pcie@2910000 { 
		reg = <0x00 0x02910000 0x00 0x1000>,

		      <0x00 0x02917000 0x00 0x400>,

		      <0x00 0x0d800000 0x00 0x00800000>,

		      <0x00 0x18000000 0x00 0x00001000>;

		      <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */

		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";

		interrupt-names = "link_state";

		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
@@ -1102,8 +1102,8 @@ pcie1_rc: pcie@2910000 { 
		device-id = <0xb012>;

		msi-map = <0x0 &gic_its 0x10000 0x10000>;

		dma-coherent;

		ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,

			 <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;

		ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */

			 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */

		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;

		status = "disabled";

	};