Commit b20b8538 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull mailbox updates from Jassi Brar:

 - aspeed: add driver and bindings for ast2700

 - broadcom: add driver and bindings for bcm74110

 - mediatek: fix RPM api usage

 - qcom: use dev_fwnode

 - pcc: support shared buffer

 - misc dt-bindings cleanup

* tag 'mailbox-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox:
  mailbox/pcc: support mailbox management of the shared buffer
  mailbox: bcm74110: Fix spelling mistake
  mailbox: bcm74110: remove unneeded semicolon
  mailbox: aspeed: add mailbox driver for AST27XX series SoC
  dt-bindings: mailbox: Add ASPEED AST2700 series SoC
  dt-bindings: mailbox: Drop consumers example DTS
  dt-bindings: mailbox: nvidia,tegra186-hsp: Use generic node name
  dt-bindings: mailbox: Correct example indentation
  dt-bindings: mailbox: ti,secure-proxy: Add missing reg maxItems
  dt-bindings: mailbox: amlogic,meson-gxbb-mhu: Add missing interrupts maxItems
  dt-bindings: mailbox: qcom-ipcc: document the Milos Inter-Processor Communication Controller
  mailbox: Add support for bcm74110
  dt-bindings: mailbox: Add support for bcm74110
  mailbox: Use dev_fwnode()
  mailbox: mtk-cmdq: Switch to pm_runtime_put_autosuspend()
parents 0227b49b 5378bdf6
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+5 −5
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@ properties:
    maxItems: 1

  interrupts:
    minItems: 3
    maxItems: 3
    description:
      Contains the interrupt information corresponding to each of the 3 links
      of MHU.
+68 −0
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/aspeed,ast2700-mailbox.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ASPEED AST2700 mailbox controller

maintainers:
  - Jammy Huang <jammy_huang@aspeedtech.com>

description: >
  ASPEED AST2700 has multiple processors that need to communicate with each
  other. The mailbox controller provides a way for these processors to send
  messages to each other. It is a hardware-based inter-processor communication
  mechanism that allows processors to send and receive messages through
  dedicated channels.

  The mailbox's tx/rx are independent, meaning that one processor can send a
  message while another processor is receiving a message simultaneously.
  There are 4 channels available for both tx and rx operations. Each channel
  has a FIFO buffer that can hold messages of a fixed size (32 bytes in this
  case).

  The mailbox controller also supports interrupt generation, allowing
  processors to notify each other when a message is available or when an event
  occurs.

properties:
  compatible:
    const: aspeed,ast2700-mailbox

  reg:
    items:
      - description: TX control register
      - description: RX control register

  reg-names:
    items:
      - const: tx
      - const: rx

  interrupts:
    maxItems: 1

  "#mbox-cells":
    const: 1

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - "#mbox-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    mailbox@12c1c200 {
        compatible = "aspeed,ast2700-mailbox";
        reg = <0x12c1c200 0x100>, <0x12c1c300 0x100>;
        reg-names = "tx", "rx";
        interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
        #mbox-cells = <1>;
    };
+64 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/brcm,bcm74110-mbox.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom BCM74110 Mailbox

maintainers:
  - Justin Chen <justin.chen@broadcom.com>
  - Florian Fainelli <florian.fainelli@broadcom.com>

description: Broadcom mailbox hardware first introduced with 74110

properties:
  compatible:
    enum:
      - brcm,bcm74110-mbox

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: RX doorbell and watermark interrupts
      - description: TX doorbell and watermark interrupts

  "#mbox-cells":
    const: 2
    description:
      The first cell is channel type and second cell is shared memory slot

  brcm,rx:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: RX Mailbox number

  brcm,tx:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: TX Mailbox number

required:
  - compatible
  - reg
  - interrupts
  - "#mbox-cells"
  - brcm,rx
  - brcm,tx

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    mailbox@a552000 {
        compatible = "brcm,bcm74110-mbox";
        reg = <0xa552000 0x1104>;
        interrupts = <GIC_SPI 0x67 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 0x66 IRQ_TYPE_LEVEL_HIGH>;
        #mbox-cells = <0x2>;
        brcm,rx = <0x7>;
        brcm,tx = <0x6>;
    };
+1 −8
Original line number Diff line number Diff line
@@ -59,9 +59,6 @@ description: |
        <dt-bindings/mailbox/tegra186-hsp.h>

properties:
  $nodename:
    pattern: "^hsp@[0-9a-f]+$"

  compatible:
    oneOf:
      - enum:
@@ -131,14 +128,10 @@ examples:
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/mailbox/tegra186-hsp.h>

    hsp_top0: hsp@3c00000 {
    mailbox@3c00000 {
        compatible = "nvidia,tegra186-hsp";
        reg = <0x03c00000 0xa0000>;
        interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "doorbell";
        #mbox-cells = <2>;
    };

    client {
        mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_CCPLEX>;
    };
+1 −8
Original line number Diff line number Diff line
@@ -251,7 +251,7 @@ examples:
  # Example apcs with msm8996
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    apcs_glb: mailbox@9820000 {
    mailbox@9820000 {
        compatible = "qcom,msm8996-apcs-hmss-global";
        reg = <0x9820000 0x1000>;

@@ -259,13 +259,6 @@ examples:
        #clock-cells = <0>;
    };

    rpm-glink {
        compatible = "qcom,glink-rpm";
        interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
        qcom,rpm-msg-ram = <&rpm_msg_ram>;
        mboxes = <&apcs_glb 0>;
    };

  # Example apcs with qcs404
  - |
    #define GCC_APSS_AHB_CLK_SRC  1
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