Commit b25bd37c authored by Tariq Toukan's avatar Tariq Toukan Committed by Saeed Mahameed
Browse files

net/mlx5: Move TISes from priv to mdev HW resources 



The transport interface send (TIS) object is responsible for performing
all transport related operations of the transmit side. Messages from
Send Queues get segmented and transmitted by the TIS including all
transport required implications, e.g. in the case of large send offload,
the TIS is responsible for the segmentation.

These are stateless objects and can be used by multiple netdevs (e.g.
representors) who share the same core device.

Providing the TISes as a service from the core layer to the netdev layer
reduces the number of replecated TIS objects (in case of multiple
netdevs), and will ease the transition to netdev with multiple mdevs.

Signed-off-by: default avatarTariq Toukan <tariqt@nvidia.com>
Reviewed-by: default avatarGal Pressman <gal@nvidia.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
parent 249e5217

drivers/net/ethernet/mellanox/mlx5/core/en.h

+11 −8
Original line number Diff line number Diff line
@@ -72,7 +72,6 @@ struct page_pool; 
#define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))

#define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))



#define MLX5E_MAX_NUM_TC	8

#define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE



#define MLX5_RX_HEADROOM NET_SKB_PAD
@@ -758,7 +757,7 @@ struct mlx5e_channel { 
	/* data path */

	struct mlx5e_rq            rq;

	struct mlx5e_xdpsq         rq_xdpsq;

	struct mlx5e_txqsq         sq[MLX5E_MAX_NUM_TC];

	struct mlx5e_txqsq         sq[MLX5_MAX_NUM_TC];

	struct mlx5e_icosq         icosq;   /* internal control operations */

	struct mlx5e_txqsq __rcu * __rcu *qos_sqs;

	bool                       xdp;
@@ -808,7 +807,7 @@ struct mlx5e_channels { 


struct mlx5e_channel_stats {

	struct mlx5e_ch_stats ch;

	struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];

	struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC];

	struct mlx5e_rq_stats rq;

	struct mlx5e_rq_stats xskrq;

	struct mlx5e_xdpsq_stats rq_xdpsq;
@@ -818,8 +817,8 @@ struct mlx5e_channel_stats { 


struct mlx5e_ptp_stats {

	struct mlx5e_ch_stats ch;

	struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];

	struct mlx5e_ptp_cq_stats cq[MLX5E_MAX_NUM_TC];

	struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC];

	struct mlx5e_ptp_cq_stats cq[MLX5_MAX_NUM_TC];

	struct mlx5e_rq_stats rq;

} ____cacheline_aligned_in_smp;
@@ -886,7 +885,6 @@ struct mlx5e_priv { 
	struct mlx5e_rq            drop_rq;



	struct mlx5e_channels      channels;

	u32                        tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC];

	struct mlx5e_rx_res       *rx_res;

	u32                       *tx_rates;
@@ -984,6 +982,8 @@ struct mlx5e_profile { 
	void	(*update_stats)(struct mlx5e_priv *priv);

	void	(*update_carrier)(struct mlx5e_priv *priv);

	int	(*max_nch_limit)(struct mlx5_core_dev *mdev);

	u32	(*get_tisn)(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv,

			    u8 lag_port, u8 tc);

	unsigned int (*stats_grps_num)(struct mlx5e_priv *priv);

	mlx5e_stats_grp_t *stats_grps;

	const struct mlx5e_rx_handlers *rx_handlers;
@@ -991,6 +991,11 @@ struct mlx5e_profile { 
	u32     features;

};



u32 mlx5e_profile_get_tisn(struct mlx5_core_dev *mdev,

			   struct mlx5e_priv *priv,

			   const struct mlx5e_profile *profile,

			   u8 lag_port, u8 tc);



#define mlx5e_profile_feature_cap(profile, feature)	\

	((profile)->features & BIT(MLX5E_PROFILE_FEATURE_##feature))
@@ -1132,8 +1137,6 @@ void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq); 
int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);

void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);



int mlx5e_create_tises(struct mlx5e_priv *priv);

void mlx5e_destroy_tises(struct mlx5e_priv *priv);

int mlx5e_update_nic_rx(struct mlx5e_priv *priv);

void mlx5e_update_carrier(struct mlx5e_priv *priv);

int mlx5e_close(struct net_device *netdev);

drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c

+4 −2
Original line number Diff line number Diff line
@@ -518,9 +518,11 @@ static int mlx5e_ptp_open_txqsqs(struct mlx5e_ptp *c, 


	for (tc = 0; tc < num_tc; tc++) {

		int txq_ix = ix_base + tc;

		u32 tisn;



		err = mlx5e_ptp_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix,

					   cparams, tc, &c->ptpsq[tc]);

		tisn = mlx5e_profile_get_tisn(c->mdev, c->priv, c->priv->profile,

					      c->lag_port, tc);

		err = mlx5e_ptp_open_txqsq(c, tisn, txq_ix, cparams, tc, &c->ptpsq[tc]);

		if (err)

			goto close_txqsq;

	}

drivers/net/ethernet/mellanox/mlx5/core/en/ptp.h

+1 −1
Original line number Diff line number Diff line
@@ -49,7 +49,7 @@ enum { 


struct mlx5e_ptp {

	/* data path */

	struct mlx5e_ptpsq         ptpsq[MLX5E_MAX_NUM_TC];

	struct mlx5e_ptpsq         ptpsq[MLX5_MAX_NUM_TC];

	struct mlx5e_rq            rq;

	struct napi_struct         napi;

	struct device             *pdev;

drivers/net/ethernet/mellanox/mlx5/core/en/qos.c

+5 −2
Original line number Diff line number Diff line
@@ -77,6 +77,7 @@ int mlx5e_open_qos_sq(struct mlx5e_priv *priv, struct mlx5e_channels *chs, 
	struct mlx5e_params *params;

	struct mlx5e_channel *c;

	struct mlx5e_txqsq *sq;

	u32 tisn;



	params = &chs->params;
@@ -126,8 +127,10 @@ int mlx5e_open_qos_sq(struct mlx5e_priv *priv, struct mlx5e_channels *chs, 
	err = mlx5e_open_cq(priv, params->tx_cq_moderation, &param_cq, &ccp, &sq->cq);

	if (err)

		goto err_free_sq;

	err = mlx5e_open_txqsq(c, priv->tisn[c->lag_port][0], txq_ix, params,

			       &param_sq, sq, 0, hw_id,



	tisn = mlx5e_profile_get_tisn(c->mdev, c->priv, c->priv->profile,

				      c->lag_port, 0);

	err = mlx5e_open_txqsq(c, tisn, txq_ix, params, &param_sq, sq, 0, hw_id,

			       priv->htb_qos_sq_stats[node_qid]);

	if (err)

		goto err_close_cq;

drivers/net/ethernet/mellanox/mlx5/core/en_common.c

+74 −0
Original line number Diff line number Diff line
@@ -74,6 +74,72 @@ int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey) 
	return err;

}



int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)

{

	void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);



	MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);



	if (mlx5_lag_is_lacp_owner(mdev))

		MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);



	return mlx5_core_create_tis(mdev, in, tisn);

}



void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)

{

	mlx5_core_destroy_tis(mdev, tisn);

}



static void mlx5e_destroy_tises(struct mlx5_core_dev *mdev, u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC])

{

	int tc, i;



	for (i = 0; i < MLX5_MAX_PORTS; i++)

		for (tc = 0; tc < MLX5_MAX_NUM_TC; tc++)

			mlx5e_destroy_tis(mdev, tisn[i][tc]);

}



static bool mlx5_lag_should_assign_affinity(struct mlx5_core_dev *mdev)

{

	return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;

}



static int mlx5e_create_tises(struct mlx5_core_dev *mdev, u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC])

{

	int tc, i;

	int err;



	for (i = 0; i < MLX5_MAX_PORTS; i++) {

		for (tc = 0; tc < MLX5_MAX_NUM_TC; tc++) {

			u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};

			void *tisc;



			tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);



			MLX5_SET(tisc, tisc, prio, tc << 1);



			if (mlx5_lag_should_assign_affinity(mdev))

				MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);



			err = mlx5e_create_tis(mdev, in, &tisn[i][tc]);

			if (err)

				goto err_close_tises;

		}

	}



	return 0;



err_close_tises:

	for (; i >= 0; i--) {

		for (tc--; tc >= 0; tc--)

			mlx5e_destroy_tis(mdev, tisn[i][tc]);

		tc = MLX5_MAX_NUM_TC;

	}



	return err;

}



int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev)

{

	struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs;
@@ -103,6 +169,11 @@ int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev) 
		goto err_destroy_mkey;

	}



	err = mlx5e_create_tises(mdev, res->tisn);

	if (err) {

		mlx5_core_err(mdev, "alloc tises failed, %d\n", err);

		goto err_destroy_bfreg;

	}

	INIT_LIST_HEAD(&res->td.tirs_list);

	mutex_init(&res->td.list_lock);
@@ -115,6 +186,8 @@ int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev) 


	return 0;



err_destroy_bfreg:

	mlx5_free_bfreg(mdev, &res->bfreg);

err_destroy_mkey:

	mlx5_core_destroy_mkey(mdev, res->mkey);

err_dealloc_transport_domain:
@@ -130,6 +203,7 @@ void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev) 


	mlx5_crypto_dek_cleanup(mdev->mlx5e_res.dek_priv);

	mdev->mlx5e_res.dek_priv = NULL;

	mlx5e_destroy_tises(mdev, res->tisn);

	mlx5_free_bfreg(mdev, &res->bfreg);

	mlx5_core_destroy_mkey(mdev, res->mkey);

	mlx5_core_dealloc_transport_domain(mdev, res->td.tdn);