Commit b2bb0573 authored by Suravee Suthikulpanit's avatar Suravee Suthikulpanit Committed by Joerg Roedel
Browse files

iommu/amd: Always enable GCR3TRPMode when supported. 



The GCR3TRPMode feature allows the DTE[GCR3TRP] field to be configured
with GPA (instead of SPA). This simplifies the implementation, and is
a pre-requisite for nested translation support.

Therefore, always enable this feature if available.

Reviewed-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Reviewed-by: default avatarNicolin Chen <nicolinc@nvidia.com>
Signed-off-by: default avatarSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: default avatarJoerg Roedel <joerg.roedel@amd.com>
parent e05698c1

drivers/iommu/amd/amd_iommu_types.h

+2 −0
Original line number Diff line number Diff line
@@ -108,6 +108,7 @@ 


/* Extended Feature 2 Bits */

#define FEATURE_SEVSNPIO_SUP	BIT_ULL(1)

#define FEATURE_GCR3TRPMODE	BIT_ULL(3)

#define FEATURE_SNPAVICSUP	GENMASK_ULL(7, 5)

#define FEATURE_SNPAVICSUP_GAM(x) \

	(FIELD_GET(FEATURE_SNPAVICSUP, x) == 0x1)
@@ -186,6 +187,7 @@ 
#define CONTROL_EPH_EN		45

#define CONTROL_XT_EN		50

#define CONTROL_INTCAPXT_EN	51

#define CONTROL_GCR3TRPMODE	58

#define CONTROL_IRTCACHEDIS	59

#define CONTROL_SNPAVIC_EN	61

drivers/iommu/amd/init.c

+8 −0
Original line number Diff line number Diff line
@@ -1122,6 +1122,14 @@ static void iommu_enable_gt(struct amd_iommu *iommu) 
		return;



	iommu_feature_enable(iommu, CONTROL_GT_EN);



	/*

	 * This feature needs to be enabled prior to a call

	 * to iommu_snp_enable(). Since this function is called

	 * in early_enable_iommu(), it is safe to enable here.

	 */

	if (check_feature2(FEATURE_GCR3TRPMODE))

		iommu_feature_enable(iommu, CONTROL_GCR3TRPMODE);

}



/* sets a specific bit in the device table entry. */