Commit b2e0059b authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/de: register wait function renames 



Do some renames on the register wait functions for clarity and brevity:

intel_de_wait_for_register	-> intel_de_wait
intel_de_wait_for_register_fw	-> intel_de_wait_fw
__intel_de_wait_for_register	-> intel_de_wait_custom

In particular, it seemed odd to have a double-underscored function be
called in a number of places.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240320160123.2904609-1-jani.nikula@intel.com
parent 1bfc03b1

drivers/gpu/drm/i915/display/intel_cx0_phy.c

+34 −34
Original line number Diff line number Diff line
@@ -151,7 +151,7 @@ static int intel_cx0_wait_for_ack(struct intel_encoder *encoder, 
	enum port port = encoder->port;

	enum phy phy = intel_encoder_to_phy(encoder);



	if (__intel_de_wait_for_register(i915,

	if (intel_de_wait_custom(i915,

				 XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane),

				 XELPDP_PORT_P2M_RESPONSE_READY,

				 XELPDP_PORT_P2M_RESPONSE_READY,
@@ -2545,7 +2545,7 @@ static void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder, 
		     intel_cx0_get_powerdown_update(lane_mask));



	/* Update Timeout Value */

	if (__intel_de_wait_for_register(i915, buf_ctl2_reg,

	if (intel_de_wait_custom(i915, buf_ctl2_reg,

				 intel_cx0_get_powerdown_update(lane_mask), 0,

				 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))

		drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
@@ -2605,7 +2605,7 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder, 
					   XELPDP_LANE_PHY_CURRENT_STATUS(1))

					: XELPDP_LANE_PHY_CURRENT_STATUS(0);



	if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(i915, port),

	if (intel_de_wait_custom(i915, XELPDP_PORT_BUF_CTL1(i915, port),

				 XELPDP_PORT_BUF_SOC_PHY_READY,

				 XELPDP_PORT_BUF_SOC_PHY_READY,

				 XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
@@ -2615,7 +2615,7 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder, 
	intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port), lane_pipe_reset,

		     lane_pipe_reset);



	if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(i915, port),

	if (intel_de_wait_custom(i915, XELPDP_PORT_BUF_CTL2(i915, port),

				 lane_phy_current_status, lane_phy_current_status,

				 XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))

		drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
@@ -2625,7 +2625,7 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder, 
		     intel_cx0_get_pclk_refclk_request(owned_lane_mask),

		     intel_cx0_get_pclk_refclk_request(lane_mask));



	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, port),

	if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, port),

				 intel_cx0_get_pclk_refclk_ack(owned_lane_mask),

				 intel_cx0_get_pclk_refclk_ack(lane_mask),

				 XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
@@ -2778,7 +2778,7 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder, 
		     intel_cx0_get_pclk_pll_request(maxpclk_lane));



	/* 10. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */

	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),

	if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),

				 intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),

				 intel_cx0_get_pclk_pll_ack(maxpclk_lane),

				 XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
@@ -2869,7 +2869,7 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder, 
	intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), val);



	/* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */

	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),

	if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),

				 XELPDP_TBT_CLOCK_ACK,

				 XELPDP_TBT_CLOCK_ACK,

				 100, 0, NULL))
@@ -2931,7 +2931,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder) 
	/*

	 * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".

	 */

	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),

	if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),

				 intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |

				 intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,

				 XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
@@ -2969,7 +2969,7 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder) 
		     XELPDP_TBT_CLOCK_REQUEST, 0);



	/* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */

	if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),

	if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),

				 XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL))

		drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",

			 encoder->base.base.id, encoder->base.name, phy_name(phy));

drivers/gpu/drm/i915/display/intel_de.h

+10 −10
Original line number Diff line number Diff line
@@ -48,21 +48,21 @@ intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set) 
}



static inline int

intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,

intel_de_wait(struct drm_i915_private *i915, i915_reg_t reg,

	      u32 mask, u32 value, unsigned int timeout)

{

	return intel_wait_for_register(&i915->uncore, reg, mask, value, timeout);

}



static inline int

intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t reg,

intel_de_wait_fw(struct drm_i915_private *i915, i915_reg_t reg,

		 u32 mask, u32 value, unsigned int timeout)

{

	return intel_wait_for_register_fw(&i915->uncore, reg, mask, value, timeout);

}



static inline int

__intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,

intel_de_wait_custom(struct drm_i915_private *i915, i915_reg_t reg,

		     u32 mask, u32 value,

		     unsigned int fast_timeout_us,

		     unsigned int slow_timeout_ms, u32 *out_value)
@@ -75,14 +75,14 @@ static inline int 
intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg,

		      u32 mask, unsigned int timeout)

{

	return intel_de_wait_for_register(i915, reg, mask, mask, timeout);

	return intel_de_wait(i915, reg, mask, mask, timeout);

}



static inline int

intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,

			u32 mask, unsigned int timeout)

{

	return intel_de_wait_for_register(i915, reg, mask, 0, timeout);

	return intel_de_wait(i915, reg, mask, 0, timeout);

}



/*

drivers/gpu/drm/i915/display/intel_display.c

+1 −2
Original line number Diff line number Diff line
@@ -383,8 +383,7 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, 
		break;

	}



	if (intel_de_wait_for_register(dev_priv, dpll_reg,

				       port_mask, expected_mask, 1000))

	if (intel_de_wait(dev_priv, dpll_reg, port_mask, expected_mask, 1000))

		drm_WARN(&dev_priv->drm, 1,

			 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",

			 dig_port->base.base.base.id, dig_port->base.base.name,

drivers/gpu/drm/i915/display/intel_display_power_well.c

+2 −2
Original line number Diff line number Diff line
@@ -1390,7 +1390,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv) 
	 * The PHY may be busy with some initial calibration and whatnot,

	 * so the power state can take a while to actually change.

	 */

	if (intel_de_wait_for_register(dev_priv, DISPLAY_PHY_STATUS,

	if (intel_de_wait(dev_priv, DISPLAY_PHY_STATUS,

			  phy_status_mask, phy_status, 10))

		drm_err(&dev_priv->drm,

			"Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",

drivers/gpu/drm/i915/display/intel_dp_aux.c

+2 −3
Original line number Diff line number Diff line
@@ -61,8 +61,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp) 
	u32 status;

	int ret;



	ret = __intel_de_wait_for_register(i915, ch_ctl,

					   DP_AUX_CH_CTL_SEND_BUSY, 0,

	ret = intel_de_wait_custom(i915, ch_ctl, DP_AUX_CH_CTL_SEND_BUSY, 0,

				   2, timeout_ms, &status);



	if (ret == -ETIMEDOUT)