Commit b2e47002 authored by FUJITA Tomonori's avatar FUJITA Tomonori Committed by David S. Miller
Browse files

rust: net::phy unified read/write API for C22 and C45 registers 



Add the unified read/write API for C22 and C45 registers. The
abstractions support access to only C22 registers now. Instead of
adding read/write_c45 methods specifically for C45, a new reg module
supports the unified API to access C22 and C45 registers with trait,
by calling an appropriate phylib functions.

Reviewed-by: default avatarTrevor Gross <tmgross@umich.edu>
Reviewed-by: default avatarBenno Lossin <benno.lossin@proton.me>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarFUJITA Tomonori <fujita.tomonori@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 7909892a

MAINTAINERS

+1 −0
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@@ -8357,6 +8357,7 @@ L: netdev@vger.kernel.org 
L:	rust-for-linux@vger.kernel.org

S:	Maintained

F:	rust/kernel/net/phy.rs

F:	rust/kernel/net/phy/reg.rs









EXEC & BINFMT API, ELF









R:	Eric Biederman <ebiederm@xmission.com>
































drivers/net/phy/ax88796b_rust.rs



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−4






























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@@ -6,7 +6,7 @@







//! C version of this driver: [`drivers/net/phy/ax88796b.c`](./ax88796b.c)









use kernel::{









    c_str,









    net::phy::{self, DeviceId, Driver},









    net::phy::{self, reg::C22, DeviceId, Driver},









    prelude::*,









    uapi,









};








@@ -24,7 +24,6 @@







    license: "GPL",









}



















const MII_BMCR: u16 = uapi::MII_BMCR as u16;









const BMCR_SPEED100: u16 = uapi::BMCR_SPEED100 as u16;









const BMCR_FULLDPLX: u16 = uapi::BMCR_FULLDPLX as u16;


















@@ -33,7 +32,7 @@







// Toggle BMCR_RESET bit off to accommodate broken AX8796B PHY implementation









// such as used on the Individual Computers' X-Surf 100 Zorro card.









fn asix_soft_reset(dev: &mut phy::Device) -> Result {









    dev.write(uapi::MII_BMCR as u16, 0)?;









    dev.write(C22::BMCR, 0)?;









    dev.genphy_soft_reset()









}


















@@ -55,7 +54,7 @@ fn read_status(dev: &mut phy::Device) -> Result<u16> {







        }









        // If MII_LPA is 0, phy_resolve_aneg_linkmode() will fail to resolve









        // linkmode so use MII_BMCR as default values.









        let ret = dev.read(MII_BMCR)?;









        let ret = dev.read(C22::BMCR)?;



















        if ret & BMCR_SPEED100 != 0 {









            dev.set_speed(uapi::SPEED_100);
































rust/kernel/net/phy.rs



+8
−23






























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@@ -9,6 +9,8 @@







use crate::{error::*, prelude::*, types::Opaque};









use core::{marker::PhantomData, ptr::addr_of_mut};



















pub mod reg;



















/// PHY state machine states.









///









/// Corresponds to the kernel's [`enum phy_state`].








@@ -177,32 +179,15 @@ pub fn set_duplex(&mut self, mode: DuplexMode) {







        unsafe { (*phydev).duplex = v };









    }



















    /// Reads a given C22 PHY register.









    /// Reads a PHY register.









    // This function reads a hardware register and updates the stats so takes `&mut self`.









    pub fn read(&mut self, regnum: u16) -> Result<u16> {









        let phydev = self.0.get();









        // SAFETY: `phydev` is pointing to a valid object by the type invariant of `Self`.









        // So it's just an FFI call, open code of `phy_read()` with a valid `phy_device` pointer









        // `phydev`.









        let ret = unsafe {









            bindings::mdiobus_read((*phydev).mdio.bus, (*phydev).mdio.addr, regnum.into())









        };









        if ret < 0 {









            Err(Error::from_errno(ret))









        } else {









            Ok(ret as u16)









        }









    pub fn read<R: reg::Register>(&mut self, reg: R) -> Result<u16> {









        reg.read(self)









    }



















    /// Writes a given C22 PHY register.









    pub fn write(&mut self, regnum: u16, val: u16) -> Result {









        let phydev = self.0.get();









        // SAFETY: `phydev` is pointing to a valid object by the type invariant of `Self`.









        // So it's just an FFI call, open code of `phy_write()` with a valid `phy_device` pointer









        // `phydev`.









        to_result(unsafe {









            bindings::mdiobus_write((*phydev).mdio.bus, (*phydev).mdio.addr, regnum.into(), val)









        })









    /// Writes a PHY register.









    pub fn write<R: reg::Register>(&mut self, reg: R, val: u16) -> Result {









        reg.write(self, val)









    }



















    /// Reads a paged register.
































rust/kernel/net/phy/reg.rs
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// SPDX-License-Identifier: GPL-2.0



















// Copyright (C) 2024 FUJITA Tomonori <fujita.tomonori@gmail.com>



















//! PHY register interfaces.









//!









//! This module provides support for accessing PHY registers in the









//! Ethernet management interface clauses 22 and 45 register namespaces, as









//! defined in IEEE 802.3.



















use super::Device;









use crate::build_assert;









use crate::error::*;









use crate::uapi;



















mod private {









    /// Marker that a trait cannot be implemented outside of this crate









    pub trait Sealed {}









}



















/// Accesses PHY registers.









///









/// This trait is used to implement the unified interface to access









/// C22 and C45 PHY registers.









///









/// # Examples









///









/// ```ignore









/// fn link_change_notify(dev: &mut Device) {









///     // read C22 BMCR register









///     dev.read(C22::BMCR);









///     // read C45 PMA/PMD control 1 register









///     dev.read(C45::new(Mmd::PMAPMD, 0));









/// }









/// ```









pub trait Register: private::Sealed {









    /// Reads a PHY register.









    fn read(&self, dev: &mut Device) -> Result<u16>;



















    /// Writes a PHY register.









    fn write(&self, dev: &mut Device, val: u16) -> Result;









}



















/// A single MDIO clause 22 register address (5 bits).









#[derive(Copy, Clone, Debug)]









pub struct C22(u8);



















impl C22 {









    /// Basic mode control.









    pub const BMCR: Self = C22(0x00);









    /// Basic mode status.









    pub const BMSR: Self = C22(0x01);









    /// PHY identifier 1.









    pub const PHYSID1: Self = C22(0x02);









    /// PHY identifier 2.









    pub const PHYSID2: Self = C22(0x03);









    /// Auto-negotiation advertisement.









    pub const ADVERTISE: Self = C22(0x04);









    /// Auto-negotiation link partner base page ability.









    pub const LPA: Self = C22(0x05);









    /// Auto-negotiation expansion.









    pub const EXPANSION: Self = C22(0x06);









    /// Auto-negotiation next page transmit.









    pub const NEXT_PAGE_TRANSMIT: Self = C22(0x07);









    /// Auto-negotiation link partner received next page.









    pub const LP_RECEIVED_NEXT_PAGE: Self = C22(0x08);









    /// Master-slave control.









    pub const MASTER_SLAVE_CONTROL: Self = C22(0x09);









    /// Master-slave status.









    pub const MASTER_SLAVE_STATUS: Self = C22(0x0a);









    /// PSE Control.









    pub const PSE_CONTROL: Self = C22(0x0b);









    /// PSE Status.









    pub const PSE_STATUS: Self = C22(0x0c);









    /// MMD Register control.









    pub const MMD_CONTROL: Self = C22(0x0d);









    /// MMD Register address data.









    pub const MMD_DATA: Self = C22(0x0e);









    /// Extended status.









    pub const EXTENDED_STATUS: Self = C22(0x0f);



















    /// Creates a new instance of `C22` with a vendor specific register.









    pub const fn vendor_specific<const N: u8>() -> Self {









        build_assert!(









            N > 0x0f && N < 0x20,









            "Vendor-specific register address must be between 16 and 31"









        );









        C22(N)









    }









}



















impl private::Sealed for C22 {}



















impl Register for C22 {









    fn read(&self, dev: &mut Device) -> Result<u16> {









        let phydev = dev.0.get();









        // SAFETY: `phydev` is pointing to a valid object by the type invariant of `Device`.









        // So it's just an FFI call, open code of `phy_read()` with a valid `phy_device` pointer









        // `phydev`.









        let ret = unsafe {









            bindings::mdiobus_read((*phydev).mdio.bus, (*phydev).mdio.addr, self.0.into())









        };









        to_result(ret)?;









        Ok(ret as u16)









    }



















    fn write(&self, dev: &mut Device, val: u16) -> Result {









        let phydev = dev.0.get();









        // SAFETY: `phydev` is pointing to a valid object by the type invariant of `Device`.









        // So it's just an FFI call, open code of `phy_write()` with a valid `phy_device` pointer









        // `phydev`.









        to_result(unsafe {









            bindings::mdiobus_write((*phydev).mdio.bus, (*phydev).mdio.addr, self.0.into(), val)









        })









    }









}



















/// A single MDIO clause 45 register device and address.









#[derive(Copy, Clone, Debug)]









pub struct Mmd(u8);



















impl Mmd {









    /// Physical Medium Attachment/Dependent.









    pub const PMAPMD: Self = Mmd(uapi::MDIO_MMD_PMAPMD as u8);









    /// WAN interface sublayer.









    pub const WIS: Self = Mmd(uapi::MDIO_MMD_WIS as u8);









    /// Physical coding sublayer.









    pub const PCS: Self = Mmd(uapi::MDIO_MMD_PCS as u8);









    /// PHY Extender sublayer.









    pub const PHYXS: Self = Mmd(uapi::MDIO_MMD_PHYXS as u8);









    /// DTE Extender sublayer.









    pub const DTEXS: Self = Mmd(uapi::MDIO_MMD_DTEXS as u8);









    /// Transmission convergence.









    pub const TC: Self = Mmd(uapi::MDIO_MMD_TC as u8);









    /// Auto negotiation.









    pub const AN: Self = Mmd(uapi::MDIO_MMD_AN as u8);









    /// Separated PMA (1).









    pub const SEPARATED_PMA1: Self = Mmd(8);









    /// Separated PMA (2).









    pub const SEPARATED_PMA2: Self = Mmd(9);









    /// Separated PMA (3).









    pub const SEPARATED_PMA3: Self = Mmd(10);









    /// Separated PMA (4).









    pub const SEPARATED_PMA4: Self = Mmd(11);









    /// OFDM PMA/PMD.









    pub const OFDM_PMAPMD: Self = Mmd(12);









    /// Power unit.









    pub const POWER_UNIT: Self = Mmd(13);









    /// Clause 22 extension.









    pub const C22_EXT: Self = Mmd(uapi::MDIO_MMD_C22EXT as u8);









    /// Vendor specific 1.









    pub const VEND1: Self = Mmd(uapi::MDIO_MMD_VEND1 as u8);









    /// Vendor specific 2.









    pub const VEND2: Self = Mmd(uapi::MDIO_MMD_VEND2 as u8);









}



















/// A single MDIO clause 45 register device and address.









///









/// Clause 45 uses a 5-bit device address to access a specific MMD within









/// a port, then a 16-bit register address to access a location within









/// that device. `C45` represents this by storing a [`Mmd`] and









/// a register number.









pub struct C45 {









    devad: Mmd,









    regnum: u16,









}



















impl C45 {









    /// Creates a new instance of `C45`.









    pub fn new(devad: Mmd, regnum: u16) -> Self {









        Self { devad, regnum }









    }









}



















impl private::Sealed for C45 {}



















impl Register for C45 {









    fn read(&self, dev: &mut Device) -> Result<u16> {









        let phydev = dev.0.get();









        // SAFETY: `phydev` is pointing to a valid object by the type invariant of `Device`.









        // So it's just an FFI call.









        let ret =









            unsafe { bindings::phy_read_mmd(phydev, self.devad.0.into(), self.regnum.into()) };









        to_result(ret)?;









        Ok(ret as u16)









    }



















    fn write(&self, dev: &mut Device, val: u16) -> Result {









        let phydev = dev.0.get();









        // SAFETY: `phydev` is pointing to a valid object by the type invariant of `Device`.









        // So it's just an FFI call.









        to_result(unsafe {









            bindings::phy_write_mmd(phydev, self.devad.0.into(), self.regnum.into(), val)









        })









    }









}
























rust/uapi/uapi_helper.h



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 */



















#include <uapi/asm-generic/ioctl.h>









#include <uapi/linux/mdio.h>









#include <uapi/linux/mii.h>









#include <uapi/linux/ethtool.h>