Unverified Commit b3510183 authored by Andreas Schwab's avatar Andreas Schwab Committed by Palmer Dabbelt
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riscv: traps_misaligned: properly sign extend value in misaligned load handler 



Add missing cast to signed long.

Signed-off-by: default avatarAndreas Schwab <schwab@suse.de>
Fixes: 956d705d ("riscv: Unaligned load/store handling for M_MODE")
Tested-by: default avatarClément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/mvmikk0goil.fsf@suse.de


Signed-off-by: default avatarPalmer Dabbelt <palmer@dabbelt.com>
parent 969f028b

arch/riscv/kernel/traps_misaligned.c

+1 −1
Original line number Diff line number Diff line
@@ -461,7 +461,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs) 
	}



	if (!fp)

		SET_RD(insn, regs, val.data_ulong << shift >> shift);

		SET_RD(insn, regs, (long)(val.data_ulong << shift) >> shift);

	else if (len == 8)

		set_f64_rd(insn, regs, val.data_u64);

	else