Commit b356ead8 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2024-05-08' of... 

Merge tag 'drm-intel-fixes-2024-05-08' of https://anongit.freedesktop.org/git/drm/drm-intel

 into drm-fixes

- Automate CCS Mode setting during engine resets (Andi)
- Fix audio time stamp programming for DP (Chaitanya)
- Fix parsing backlight BDB data (Karthikeyan)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZjvTVEmQeVKVB2jx@intel.com
parents dd5a440a 43b26bdd

drivers/gpu/drm/i915/display/intel_audio.c

+8 −105
Original line number Diff line number Diff line
@@ -76,19 +76,6 @@ struct intel_audio_funcs { 
				       struct intel_crtc_state *crtc_state);

};



/* DP N/M table */

#define LC_810M	810000

#define LC_540M	540000

#define LC_270M	270000

#define LC_162M	162000



struct dp_aud_n_m {

	int sample_rate;

	int clock;

	u16 m;

	u16 n;

};



struct hdmi_aud_ncts {

	int sample_rate;

	int clock;
@@ -96,60 +83,6 @@ struct hdmi_aud_ncts { 
	int cts;

};



/* Values according to DP 1.4 Table 2-104 */

static const struct dp_aud_n_m dp_aud_n_m[] = {

	{ 32000, LC_162M, 1024, 10125 },

	{ 44100, LC_162M, 784, 5625 },

	{ 48000, LC_162M, 512, 3375 },

	{ 64000, LC_162M, 2048, 10125 },

	{ 88200, LC_162M, 1568, 5625 },

	{ 96000, LC_162M, 1024, 3375 },

	{ 128000, LC_162M, 4096, 10125 },

	{ 176400, LC_162M, 3136, 5625 },

	{ 192000, LC_162M, 2048, 3375 },

	{ 32000, LC_270M, 1024, 16875 },

	{ 44100, LC_270M, 784, 9375 },

	{ 48000, LC_270M, 512, 5625 },

	{ 64000, LC_270M, 2048, 16875 },

	{ 88200, LC_270M, 1568, 9375 },

	{ 96000, LC_270M, 1024, 5625 },

	{ 128000, LC_270M, 4096, 16875 },

	{ 176400, LC_270M, 3136, 9375 },

	{ 192000, LC_270M, 2048, 5625 },

	{ 32000, LC_540M, 1024, 33750 },

	{ 44100, LC_540M, 784, 18750 },

	{ 48000, LC_540M, 512, 11250 },

	{ 64000, LC_540M, 2048, 33750 },

	{ 88200, LC_540M, 1568, 18750 },

	{ 96000, LC_540M, 1024, 11250 },

	{ 128000, LC_540M, 4096, 33750 },

	{ 176400, LC_540M, 3136, 18750 },

	{ 192000, LC_540M, 2048, 11250 },

	{ 32000, LC_810M, 1024, 50625 },

	{ 44100, LC_810M, 784, 28125 },

	{ 48000, LC_810M, 512, 16875 },

	{ 64000, LC_810M, 2048, 50625 },

	{ 88200, LC_810M, 1568, 28125 },

	{ 96000, LC_810M, 1024, 16875 },

	{ 128000, LC_810M, 4096, 50625 },

	{ 176400, LC_810M, 3136, 28125 },

	{ 192000, LC_810M, 2048, 16875 },

};



static const struct dp_aud_n_m *

audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate)

{

	int i;



	for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {

		if (rate == dp_aud_n_m[i].sample_rate &&

		    crtc_state->port_clock == dp_aud_n_m[i].clock)

			return &dp_aud_n_m[i];

	}



	return NULL;

}



static const struct {

	int clock;

	u32 config;
@@ -387,47 +320,17 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder, 
			   const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	struct i915_audio_component *acomp = i915->display.audio.component;

	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;

	enum port port = encoder->port;

	const struct dp_aud_n_m *nm;

	int rate;

	u32 tmp;



	rate = acomp ? acomp->aud_sample_rate[port] : 0;

	nm = audio_config_dp_get_n_m(crtc_state, rate);

	if (nm)

		drm_dbg_kms(&i915->drm, "using Maud %u, Naud %u\n", nm->m,

			    nm->n);

	else

		drm_dbg_kms(&i915->drm, "using automatic Maud, Naud\n");



	tmp = intel_de_read(i915, HSW_AUD_CFG(cpu_transcoder));

	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;

	tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;

	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;

	tmp |= AUD_CONFIG_N_VALUE_INDEX;



	if (nm) {

		tmp &= ~AUD_CONFIG_N_MASK;

		tmp |= AUD_CONFIG_N(nm->n);

		tmp |= AUD_CONFIG_N_PROG_ENABLE;

	}



	intel_de_write(i915, HSW_AUD_CFG(cpu_transcoder), tmp);



	tmp = intel_de_read(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));

	tmp &= ~AUD_CONFIG_M_MASK;

	tmp &= ~AUD_M_CTS_M_VALUE_INDEX;

	tmp &= ~AUD_M_CTS_M_PROG_ENABLE;



	if (nm) {

		tmp |= nm->m;

		tmp |= AUD_M_CTS_M_VALUE_INDEX;

		tmp |= AUD_M_CTS_M_PROG_ENABLE;

	}

	/* Enable time stamps. Let HW calculate Maud/Naud values */

	intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder),

		     AUD_CONFIG_N_VALUE_INDEX |

		     AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK |

		     AUD_CONFIG_UPPER_N_MASK |

		     AUD_CONFIG_LOWER_N_MASK |

		     AUD_CONFIG_N_PROG_ENABLE,

		     AUD_CONFIG_N_VALUE_INDEX);



	intel_de_write(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);

}



static void

drivers/gpu/drm/i915/display/intel_bios.c

+4 −15
Original line number Diff line number Diff line
@@ -1042,23 +1042,12 @@ parse_lfp_backlight(struct drm_i915_private *i915, 
	panel->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;

	panel->vbt.backlight.controller = 0;

	if (i915->display.vbt.version >= 191) {

		size_t exp_size;



		if (i915->display.vbt.version >= 236)

			exp_size = sizeof(struct bdb_lfp_backlight_data);

		else if (i915->display.vbt.version >= 234)

			exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_234;

		else

			exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_191;



		if (get_blocksize(backlight_data) >= exp_size) {

		const struct lfp_backlight_control_method *method;



		method = &backlight_data->backlight_control[panel_type];

		panel->vbt.backlight.type = method->type;

		panel->vbt.backlight.controller = method->controller;

	}

	}



	panel->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;

	panel->vbt.backlight.active_low_pwm = entry->active_low_pwm;

drivers/gpu/drm/i915/display/intel_vbt_defs.h

+0 −5
Original line number Diff line number Diff line
@@ -897,11 +897,6 @@ struct lfp_brightness_level { 
	u16 reserved;

} __packed;



#define EXP_BDB_LFP_BL_DATA_SIZE_REV_191 \

	offsetof(struct bdb_lfp_backlight_data, brightness_level)

#define EXP_BDB_LFP_BL_DATA_SIZE_REV_234 \

	offsetof(struct bdb_lfp_backlight_data, brightness_precision_bits)



struct bdb_lfp_backlight_data {

	u8 entry_size;

	struct lfp_backlight_data_entry data[16];

drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c

+3 −3
Original line number Diff line number Diff line
@@ -8,14 +8,14 @@ 
#include "intel_gt_ccs_mode.h"

#include "intel_gt_regs.h"



void intel_gt_apply_ccs_mode(struct intel_gt *gt)

unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt)

{

	int cslice;

	u32 mode = 0;

	int first_ccs = __ffs(CCS_MASK(gt));



	if (!IS_DG2(gt->i915))

		return;

		return 0;



	/* Build the value for the fixed CCS load balancing */

	for (cslice = 0; cslice < I915_MAX_CCS; cslice++) {
@@ -35,5 +35,5 @@ void intel_gt_apply_ccs_mode(struct intel_gt *gt) 
						     XEHP_CCS_MODE_CSLICE_MASK);

	}



	intel_uncore_write(gt->uncore, XEHP_CCS_MODE, mode);

	return mode;

}

drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h

+1 −1
Original line number Diff line number Diff line
@@ -8,6 +8,6 @@ 


struct intel_gt;



void intel_gt_apply_ccs_mode(struct intel_gt *gt);

unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt);



#endif /* __INTEL_GT_CCS_MODE_H__ */