Commit b372359f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'perf-urgent-2025-04-18' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 perf event fixes from Ingo Molnar:
 "Miscellaneous fixes and a hardware-enabling change:

   - Fix Intel uncore PMU IIO free running counters on SPR, ICX and SNR
     systems

   - Fix Intel PEBS buffer overflow handling

   - Fix skid in Intel PEBS sampling of user-space general purpose
     registers

   - Enable Panther Lake PMU support - similar to Lunar Lake"

* tag 'perf-urgent-2025-04-18' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/x86/intel: Add Panther Lake support
  perf/x86/intel: Allow to update user space GPRs from PEBS records
  perf/x86/intel: Don't clear perf metrics overflow bit unconditionally
  perf/x86/intel/uncore: Fix the scale of IIO free running counters on SPR
  perf/x86/intel/uncore: Fix the scale of IIO free running counters on ICX
  perf/x86/intel/uncore: Fix the scale of IIO free running counters on SNR
parents b0c3bc35 7950de14

arch/x86/events/intel/core.c

+20 −4
Original line number Diff line number Diff line
@@ -3049,7 +3049,6 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status) 
	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);

	int bit;

	int handled = 0;

	u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);



	inc_irq_stat(apic_perf_irqs);
@@ -3093,7 +3092,6 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status) 
		handled++;

		x86_pmu_handle_guest_pebs(regs, &data);

		static_call(x86_pmu_drain_pebs)(regs, &data);

		status &= intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;



		/*

		 * PMI throttle may be triggered, which stops the PEBS event.
@@ -3104,6 +3102,15 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status) 
		 */

		if (pebs_enabled != cpuc->pebs_enabled)

			wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);



		/*

		 * Above PEBS handler (PEBS counters snapshotting) has updated fixed

		 * counter 3 and perf metrics counts if they are in counter group,

		 * unnecessary to update again.

		 */

		if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] &&

		    is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS]))

			status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT;

	}



	/*
@@ -3123,6 +3130,8 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status) 
		static_call(intel_pmu_update_topdown_event)(NULL, NULL);

	}



	status &= hybrid(cpuc->pmu, intel_ctrl);



	/*

	 * Checkpointed counters can lead to 'spurious' PMIs because the

	 * rollback caused by the PMI will have cleared the overflow status
@@ -7305,8 +7314,17 @@ __init int intel_pmu_init(void) 
		name = "meteorlake_hybrid";

		break;



	case INTEL_PANTHERLAKE_L:

		pr_cont("Pantherlake Hybrid events, ");

		name = "pantherlake_hybrid";

		goto lnl_common;



	case INTEL_LUNARLAKE_M:

	case INTEL_ARROWLAKE:

		pr_cont("Lunarlake Hybrid events, ");

		name = "lunarlake_hybrid";



	lnl_common:

		intel_pmu_init_hybrid(hybrid_big_small);



		x86_pmu.pebs_latency_data = lnl_latency_data;
@@ -7328,8 +7346,6 @@ __init int intel_pmu_init(void) 
		intel_pmu_init_skt(&pmu->pmu);



		intel_pmu_pebs_data_source_lnl();

		pr_cont("Lunarlake Hybrid events, ");

		name = "lunarlake_hybrid";

		break;



	case INTEL_ARROWLAKE_H:

arch/x86/events/intel/ds.c

+5 −3
Original line number Diff line number Diff line
@@ -1399,8 +1399,10 @@ static u64 pebs_update_adaptive_cfg(struct perf_event *event) 
	 * + precise_ip < 2 for the non event IP

	 * + For RTM TSX weight we need GPRs for the abort code.

	 */

	gprs = (sample_type & PERF_SAMPLE_REGS_INTR) &&

	       (attr->sample_regs_intr & PEBS_GP_REGS);

	gprs = ((sample_type & PERF_SAMPLE_REGS_INTR) &&

		(attr->sample_regs_intr & PEBS_GP_REGS)) ||

	       ((sample_type & PERF_SAMPLE_REGS_USER) &&

		(attr->sample_regs_user & PEBS_GP_REGS));



	tsx_weight = (sample_type & PERF_SAMPLE_WEIGHT_TYPE) &&

		     ((attr->config & INTEL_ARCH_EVENT_MASK) ==
@@ -2123,7 +2125,7 @@ static void setup_pebs_adaptive_sample_data(struct perf_event *event, 
			regs->flags &= ~PERF_EFLAGS_EXACT;

		}



		if (sample_type & PERF_SAMPLE_REGS_INTR)

		if (sample_type & (PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER))

			adaptive_pebs_save_regs(regs, gprs);

	}

arch/x86/events/intel/uncore_snbep.c

+10 −97
Original line number Diff line number Diff line
@@ -4891,28 +4891,28 @@ static struct uncore_event_desc snr_uncore_iio_freerunning_events[] = { 
	INTEL_UNCORE_EVENT_DESC(ioclk,			"event=0xff,umask=0x10"),

	/* Free-Running IIO BANDWIDTH IN Counters */

	INTEL_UNCORE_EVENT_DESC(bw_in_port0,		"event=0xff,umask=0x20"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port0.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port0.scale,	"3.0517578125e-5"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port0.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port1,		"event=0xff,umask=0x21"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port1.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port1.scale,	"3.0517578125e-5"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port1.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port2,		"event=0xff,umask=0x22"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port2.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port2.scale,	"3.0517578125e-5"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port2.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port3,		"event=0xff,umask=0x23"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port3.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port3.scale,	"3.0517578125e-5"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port3.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port4,		"event=0xff,umask=0x24"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port4.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port4.scale,	"3.0517578125e-5"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port4.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port5,		"event=0xff,umask=0x25"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port5.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port5.scale,	"3.0517578125e-5"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port5.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port6,		"event=0xff,umask=0x26"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port6.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port6.scale,	"3.0517578125e-5"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port6.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port7,		"event=0xff,umask=0x27"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port7.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port7.scale,	"3.0517578125e-5"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port7.unit,	"MiB"),

	{ /* end: all zeroes */ },

};
@@ -5485,37 +5485,6 @@ static struct freerunning_counters icx_iio_freerunning[] = { 
	[ICX_IIO_MSR_BW_IN]	= { 0xaa0, 0x1, 0x10, 8, 48, icx_iio_bw_freerunning_box_offsets },

};



static struct uncore_event_desc icx_uncore_iio_freerunning_events[] = {

	/* Free-Running IIO CLOCKS Counter */

	INTEL_UNCORE_EVENT_DESC(ioclk,			"event=0xff,umask=0x10"),

	/* Free-Running IIO BANDWIDTH IN Counters */

	INTEL_UNCORE_EVENT_DESC(bw_in_port0,		"event=0xff,umask=0x20"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port0.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port0.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port1,		"event=0xff,umask=0x21"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port1.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port1.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port2,		"event=0xff,umask=0x22"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port2.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port2.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port3,		"event=0xff,umask=0x23"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port3.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port3.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port4,		"event=0xff,umask=0x24"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port4.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port4.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port5,		"event=0xff,umask=0x25"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port5.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port5.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port6,		"event=0xff,umask=0x26"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port6.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port6.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port7,		"event=0xff,umask=0x27"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port7.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port7.unit,	"MiB"),

	{ /* end: all zeroes */ },

};



static struct intel_uncore_type icx_uncore_iio_free_running = {

	.name			= "iio_free_running",

	.num_counters		= 9,
@@ -5523,7 +5492,7 @@ static struct intel_uncore_type icx_uncore_iio_free_running = { 
	.num_freerunning_types	= ICX_IIO_FREERUNNING_TYPE_MAX,

	.freerunning		= icx_iio_freerunning,

	.ops			= &skx_uncore_iio_freerunning_ops,

	.event_descs		= icx_uncore_iio_freerunning_events,

	.event_descs		= snr_uncore_iio_freerunning_events,

	.format_group		= &skx_uncore_iio_freerunning_format_group,

};
@@ -6320,69 +6289,13 @@ static struct freerunning_counters spr_iio_freerunning[] = { 
	[SPR_IIO_MSR_BW_OUT]	= { 0x3808, 0x1, 0x10, 8, 48 },

};



static struct uncore_event_desc spr_uncore_iio_freerunning_events[] = {

	/* Free-Running IIO CLOCKS Counter */

	INTEL_UNCORE_EVENT_DESC(ioclk,			"event=0xff,umask=0x10"),

	/* Free-Running IIO BANDWIDTH IN Counters */

	INTEL_UNCORE_EVENT_DESC(bw_in_port0,		"event=0xff,umask=0x20"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port0.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port0.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port1,		"event=0xff,umask=0x21"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port1.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port1.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port2,		"event=0xff,umask=0x22"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port2.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port2.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port3,		"event=0xff,umask=0x23"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port3.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port3.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port4,		"event=0xff,umask=0x24"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port4.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port4.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port5,		"event=0xff,umask=0x25"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port5.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port5.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port6,		"event=0xff,umask=0x26"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port6.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port6.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port7,		"event=0xff,umask=0x27"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port7.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_in_port7.unit,	"MiB"),

	/* Free-Running IIO BANDWIDTH OUT Counters */

	INTEL_UNCORE_EVENT_DESC(bw_out_port0,		"event=0xff,umask=0x30"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port0.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port0.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port1,		"event=0xff,umask=0x31"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port1.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port1.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port2,		"event=0xff,umask=0x32"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port2.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port2.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port3,		"event=0xff,umask=0x33"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port3.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port3.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port4,		"event=0xff,umask=0x34"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port4.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port4.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port5,		"event=0xff,umask=0x35"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port5.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port5.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port6,		"event=0xff,umask=0x36"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port6.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port6.unit,	"MiB"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port7,		"event=0xff,umask=0x37"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port7.scale,	"3.814697266e-6"),

	INTEL_UNCORE_EVENT_DESC(bw_out_port7.unit,	"MiB"),

	{ /* end: all zeroes */ },

};



static struct intel_uncore_type spr_uncore_iio_free_running = {

	.name			= "iio_free_running",

	.num_counters		= 17,

	.num_freerunning_types	= SPR_IIO_FREERUNNING_TYPE_MAX,

	.freerunning		= spr_iio_freerunning,

	.ops			= &skx_uncore_iio_freerunning_ops,

	.event_descs		= spr_uncore_iio_freerunning_events,

	.event_descs		= snr_uncore_iio_freerunning_events,

	.format_group		= &skx_uncore_iio_freerunning_format_group,

};