Commit b3b26c98 authored by Karol Kolacinski's avatar Karol Kolacinski Committed by Tony Nguyen
Browse files

ice: use designated initializers for TSPLL consts 



Instead of multiple comments, use designated initializers for TSPLL
consts.

Adjust ice_tspll_params_e82x fields sizes.

Reviewed-by: default avatarMichal Kubiak <michal.kubiak@intel.com>
Reviewed-by: default avatarMilena Olech <milena.olech@intel.com>
Signed-off-by: default avatarKarol Kolacinski <karol.kolacinski@intel.com>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
parent b14b2d07

drivers/net/ethernet/intel/ice/ice_tspll.c

+30 −65
Original line number Diff line number Diff line
@@ -7,76 +7,41 @@ 


static const struct

ice_tspll_params_e82x e82x_tspll_params[NUM_ICE_TSPLL_FREQ] = {

	/* ICE_TSPLL_FREQ_25_000 -> 25 MHz */

	{

		/* refclk_pre_div */

		1,

		/* feedback_div */

		197,

		/* frac_n_div */

		2621440,

		/* post_pll_div */

		6,

	[ICE_TSPLL_FREQ_25_000] = {

		.refclk_pre_div = 1,

		.post_pll_div = 6,

		.feedback_div = 197,

		.frac_n_div = 2621440,

	},



	/* ICE_TSPLL_FREQ_122_880 -> 122.88 MHz */

	{

		/* refclk_pre_div */

		5,

		/* feedback_div */

		223,

		/* frac_n_div */

		524288,

		/* post_pll_div */

		7,

	[ICE_TSPLL_FREQ_122_880] = {

		.refclk_pre_div = 5,

		.post_pll_div = 7,

		.feedback_div = 223,

		.frac_n_div = 524288

	},



	/* ICE_TSPLL_FREQ_125_000 -> 125 MHz */

	{

		/* refclk_pre_div */

		5,

		/* feedback_div */

		223,

		/* frac_n_div */

		524288,

		/* post_pll_div */

		7,

	[ICE_TSPLL_FREQ_125_000] = {

		.refclk_pre_div = 5,

		.post_pll_div = 7,

		.feedback_div = 223,

		.frac_n_div = 524288

	},



	/* ICE_TSPLL_FREQ_153_600 -> 153.6 MHz */

	{

		/* refclk_pre_div */

		5,

		/* feedback_div */

		159,

		/* frac_n_div */

		1572864,

		/* post_pll_div */

		6,

	[ICE_TSPLL_FREQ_153_600] = {

		.refclk_pre_div = 5,

		.post_pll_div = 6,

		.feedback_div = 159,

		.frac_n_div = 1572864

	},



	/* ICE_TSPLL_FREQ_156_250 -> 156.25 MHz */

	{

		/* refclk_pre_div */

		5,

		/* feedback_div */

		159,

		/* frac_n_div */

		1572864,

		/* post_pll_div */

		6,

	[ICE_TSPLL_FREQ_156_250] = {

		.refclk_pre_div = 5,

		.post_pll_div = 6,

		.feedback_div = 159,

		.frac_n_div = 1572864

	},



	/* ICE_TSPLL_FREQ_245_760 -> 245.76 MHz */

	{

		/* refclk_pre_div */

		10,

		/* feedback_div */

		223,

		/* frac_n_div */

		524288,

		/* post_pll_div */

		7,

	[ICE_TSPLL_FREQ_245_760] = {

		.refclk_pre_div = 10,

		.post_pll_div = 7,

		.feedback_div = 223,

		.frac_n_div = 524288

	},

};

drivers/net/ethernet/intel/ice/ice_tspll.h

+4 −4
Original line number Diff line number Diff line
@@ -7,18 +7,18 @@ 
/**

 * struct ice_tspll_params_e82x - E82X TSPLL parameters

 * @refclk_pre_div: Reference clock pre-divisor

 * @post_pll_div: Post PLL divisor

 * @feedback_div: Feedback divisor

 * @frac_n_div: Fractional divisor

 * @post_pll_div: Post PLL divisor

 *

 * Clock Generation Unit parameters used to program the PLL based on the

 * selected TIME_REF/TCXO frequency.

 */

struct ice_tspll_params_e82x {

	u32 refclk_pre_div;

	u32 feedback_div;

	u8 refclk_pre_div;

	u8 post_pll_div;

	u8 feedback_div;

	u32 frac_n_div;

	u32 post_pll_div;

};



#define ICE_TSPLL_CK_REFCLKFREQ_E825		0x1F