Commit b3e29b6e authored by Rob Herring (Arm)'s avatar Rob Herring (Arm)
Browse files

dt-bindings: npu: Add Arm Ethos-U65/U85



Add a binding schema for Arm Ethos-U65/U85 NPU. The Arm Ethos-U NPUs are
designed for edge AI inference applications.

Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarFrank Li <Frank.Li@nxp.com>
Acked-by: default avatarTomeu Vizoso <tomeu@tomeuvizoso.net>
Link: https://patch.msgid.link/20251020-ethos-v6-1-ecebc383c4b7@kernel.org


Signed-off-by: default avatarRob Herring (Arm) <robh@kernel.org>
parent 81233d54
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/npu/arm,ethos.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Arm Ethos U65/U85

maintainers:
  - Rob Herring <robh@kernel.org>

description: >
  The Arm Ethos-U NPUs are designed for IoT inference applications. The NPUs
  can accelerate 8-bit and 16-bit integer quantized networks:

    Transformer networks (U85 only)
    Convolutional Neural Networks (CNN)
    Recurrent Neural Networks (RNN)

  Further documentation is available here:

    U65 TRM: https://developer.arm.com/documentation/102023/
    U85 TRM: https://developer.arm.com/documentation/102685/

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - fsl,imx93-npu
          - const: arm,ethos-u65
      - items:
          - {}
          - const: arm,ethos-u85

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: core
      - const: apb

  power-domains:
    maxItems: 1

  sram:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/imx93-clock.h>

    npu@4a900000 {
        compatible = "fsl,imx93-npu", "arm,ethos-u65";
        reg = <0x4a900000 0x1000>;
        interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
        power-domains = <&mlmix>;
        clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
        clock-names = "core", "apb";
        sram = <&sram>;
    };
...