Commit b40c8377 authored by Paloma Arellano's avatar Paloma Arellano Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: modify encoder programming for CDM over DP 



Adjust the encoder format programming in the case of video mode for DP
to accommodate CDM related changes.

Changes in v4:
	- Remove hw_cdm check in dpu_encoder_needs_periph_flush()
	- Remove hw_cdm check when getting the fmt_fourcc in
	  dpu_encoder_phys_vid_enable()

Changes in v2:
	- Move timing engine programming to a separate patch from this
	  one
	- Move update_pending_flush_periph() invocation completely to
	  this patch
	- Change the logic of dpu_encoder_get_drm_fmt() so that it only
	  calls drm_mode_is_420_only() instead of doing additional
	  unnecessary checks
	- Create new functions msm_dp_needs_periph_flush() and it's
	  supporting function dpu_encoder_needs_periph_flush() to check
	  if the mode is YUV420 and VSC SDP is enabled before doing a
	  peripheral flush

Signed-off-by: default avatarPaloma Arellano <quic_parellan@quicinc.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/579641/
Link: https://lore.kernel.org/r/20240222194025.25329-17-quic_parellan@quicinc.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 21497a46

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

+35 −0
Original line number Diff line number Diff line
@@ -218,6 +218,41 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = { 
	15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10

};



u32 dpu_encoder_get_drm_fmt(struct dpu_encoder_phys *phys_enc)

{

	struct drm_encoder *drm_enc;

	struct dpu_encoder_virt *dpu_enc;

	struct drm_display_info *info;

	struct drm_display_mode *mode;



	drm_enc = phys_enc->parent;

	dpu_enc = to_dpu_encoder_virt(drm_enc);

	info = &dpu_enc->connector->display_info;

	mode = &phys_enc->cached_mode;



	if (drm_mode_is_420_only(info, mode))

		return DRM_FORMAT_YUV420;



	return DRM_FORMAT_RGB888;

}



bool dpu_encoder_needs_periph_flush(struct dpu_encoder_phys *phys_enc)

{

	struct drm_encoder *drm_enc;

	struct dpu_encoder_virt *dpu_enc;

	struct msm_display_info *disp_info;

	struct msm_drm_private *priv;

	struct drm_display_mode *mode;



	drm_enc = phys_enc->parent;

	dpu_enc = to_dpu_encoder_virt(drm_enc);

	disp_info = &dpu_enc->disp_info;

	priv = drm_enc->dev->dev_private;

	mode = &phys_enc->cached_mode;



	return phys_enc->hw_intf->cap->type == INTF_DP &&

	       msm_dp_needs_periph_flush(priv->dp[disp_info->h_tile_instance[0]], mode);

}



bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc)

{

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h

+13 −0
Original line number Diff line number Diff line
@@ -334,6 +334,19 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( 
 */

unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);



/**

 * dpu_encoder_get_drm_fmt - return DRM fourcc format

 * @phys_enc: Pointer to physical encoder structure

 */

u32 dpu_encoder_get_drm_fmt(struct dpu_encoder_phys *phys_enc);



/**

 * dpu_encoder_needs_periph_flush - return true if physical encoder requires

 *	peripheral flush

 * @phys_enc: Pointer to physical encoder structure

 */

bool dpu_encoder_needs_periph_flush(struct dpu_encoder_phys *phys_enc);



/**

 * dpu_encoder_helper_split_config - split display configuration helper function

 *	This helper function may be used by physical encoders to configure

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

+16 −0
Original line number Diff line number Diff line
@@ -405,8 +405,12 @@ static int dpu_encoder_phys_vid_control_vblank_irq( 
static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)

{

	struct dpu_hw_ctl *ctl;

	const struct dpu_format *fmt;

	u32 fmt_fourcc;



	ctl = phys_enc->hw_ctl;

	fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc);

	fmt = dpu_get_dpu_format(fmt_fourcc);



	DPU_DEBUG_VIDENC(phys_enc, "\n");
@@ -415,6 +419,8 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) 


	dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx);



	dpu_encoder_helper_phys_setup_cdm(phys_enc, fmt, CDM_CDWN_OUTPUT_HDMI);



	dpu_encoder_phys_vid_setup_timing_engine(phys_enc);



	/*
@@ -430,6 +436,16 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) 
	if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d)

		ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx);



	if (ctl->ops.update_pending_flush_cdm && phys_enc->hw_cdm)

		ctl->ops.update_pending_flush_cdm(ctl, phys_enc->hw_cdm->idx);



	/*

	 * Peripheral flush must be updated whenever flushing SDP packets is needed.

	 * SDP packets are required for any YUV format (YUV420, YUV422, YUV444).

	 */

	if (ctl->ops.update_pending_flush_periph && dpu_encoder_needs_periph_flush(phys_enc))

		ctl->ops.update_pending_flush_periph(ctl, phys_enc->hw_intf->idx);



skip_flush:

	DPU_DEBUG_VIDENC(phys_enc,

		"update pending flush ctl %d intf %d\n",

drivers/gpu/drm/msm/dp/dp_display.c

+18 −0
Original line number Diff line number Diff line
@@ -1376,6 +1376,24 @@ void __exit msm_dp_unregister(void) 
	platform_driver_unregister(&dp_display_driver);

}



bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display,

			       const struct drm_display_mode *mode)

{

	struct dp_display_private *dp;

	const struct drm_display_info *info;



	dp = container_of(dp_display, struct dp_display_private, dp_display);

	info = &dp_display->connector->display_info;



	return dp->panel->vsc_sdp_supported && drm_mode_is_420_only(info, mode);

}



bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display,

			       const struct drm_display_mode *mode)

{

	return msm_dp_is_yuv_420_enabled(dp_display, mode);

}



bool msm_dp_wide_bus_available(const struct msm_dp *dp_display)

{

	struct dp_display_private *dp;

drivers/gpu/drm/msm/msm_drv.h

+16 −1
Original line number Diff line number Diff line
@@ -387,7 +387,10 @@ void __exit msm_dp_unregister(void); 
int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,

			 struct drm_encoder *encoder);

void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display);



bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display,

			       const struct drm_display_mode *mode);

bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display,

			       const struct drm_display_mode *mode);

bool msm_dp_wide_bus_available(const struct msm_dp *dp_display);



#else
@@ -409,6 +412,18 @@ static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm 
{

}



static inline bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display,

					     const struct drm_display_mode *mode)

{

	return false;

}



static inline bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display,

					     const struct drm_display_mode *mode)

{

	return false;

}



static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display)

{

	return false;