Commit b456259e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mmc-v6.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc 

Pull MMC fixes from Ulf Hansson:
 "MMC core:
   - Fix broken cache-flush support for Micron eMMCs
   - Revert 'mmc: core: Capture correct oemid-bits for eMMC cards'

  MMC host:
   - sdhci_am654: Fix TAP value parsing for legacy speed mode
   - sdhci-pci-gli: Fix support for ASPM mode for GL9755/GL9750
   - vub300: Fix an error path in probe"

* tag 'mmc-v6.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc:
  mmc: sdhci-pci-gli: GL9750: Mask the replay timer timeout of AER
  mmc: sdhci-pci-gli: GL9755: Mask the replay timer timeout of AER
  Revert "mmc: core: Capture correct oemid-bits for eMMC cards"
  mmc: vub300: fix an error code
  mmc: Add quirk MMC_QUIRK_BROKEN_CACHE_FLUSH for Micron eMMC Q2J54A
  mmc: sdhci_am654: fix start loop index for TAP value parsing
parents b077b7ee 015c9cbc

drivers/mmc/core/block.c

+3 −1
Original line number Diff line number Diff line
@@ -2381,8 +2381,10 @@ enum mmc_issued mmc_blk_mq_issue_rq(struct mmc_queue *mq, struct request *req) 
			}

			ret = mmc_blk_cqe_issue_flush(mq, req);

			break;

		case REQ_OP_READ:

		case REQ_OP_WRITE:

			card->written_flag = true;

			fallthrough;

		case REQ_OP_READ:

			if (host->cqe_enabled)

				ret = mmc_blk_cqe_issue_rw_rq(mq, req);

			else

drivers/mmc/core/card.h

+4 −0
Original line number Diff line number Diff line
@@ -280,4 +280,8 @@ static inline int mmc_card_broken_sd_cache(const struct mmc_card *c) 
	return c->quirks & MMC_QUIRK_BROKEN_SD_CACHE;

}



static inline int mmc_card_broken_cache_flush(const struct mmc_card *c)

{

	return c->quirks & MMC_QUIRK_BROKEN_CACHE_FLUSH;

}

#endif

drivers/mmc/core/mmc.c

+7 −3
Original line number Diff line number Diff line
@@ -104,7 +104,7 @@ static int mmc_decode_cid(struct mmc_card *card) 
	case 3: /* MMC v3.1 - v3.3 */

	case 4: /* MMC v4 */

		card->cid.manfid	= UNSTUFF_BITS(resp, 120, 8);

		card->cid.oemid		= UNSTUFF_BITS(resp, 104, 8);

		card->cid.oemid		= UNSTUFF_BITS(resp, 104, 16);

		card->cid.prod_name[0]	= UNSTUFF_BITS(resp, 96, 8);

		card->cid.prod_name[1]	= UNSTUFF_BITS(resp, 88, 8);

		card->cid.prod_name[2]	= UNSTUFF_BITS(resp, 80, 8);
@@ -2086,13 +2086,17 @@ static int _mmc_flush_cache(struct mmc_host *host) 
{

	int err = 0;



	if (mmc_card_broken_cache_flush(host->card) && !host->card->written_flag)

		return 0;



	if (_mmc_cache_enabled(host)) {

		err = mmc_switch(host->card, EXT_CSD_CMD_SET_NORMAL,

				 EXT_CSD_FLUSH_CACHE, 1,

				 CACHE_FLUSH_TIMEOUT_MS);

		if (err)

			pr_err("%s: cache flush error %d\n",

			       mmc_hostname(host), err);

			pr_err("%s: cache flush error %d\n", mmc_hostname(host), err);

		else

			host->card->written_flag = false;

	}



	return err;

drivers/mmc/core/quirks.h

+4 −3
Original line number Diff line number Diff line
@@ -110,11 +110,12 @@ static const struct mmc_fixup __maybe_unused mmc_blk_fixups[] = { 
		  MMC_QUIRK_TRIM_BROKEN),



	/*

	 * Micron MTFC4GACAJCN-1M advertises TRIM but it does not seems to

	 * support being used to offload WRITE_ZEROES.

	 * Micron MTFC4GACAJCN-1M supports TRIM but does not appear to support

	 * WRITE_ZEROES offloading. It also supports caching, but the cache can

	 * only be flushed after a write has occurred.

	 */

	MMC_FIXUP("Q2J54A", CID_MANFID_MICRON, 0x014e, add_quirk_mmc,

		  MMC_QUIRK_TRIM_BROKEN),

		  MMC_QUIRK_TRIM_BROKEN | MMC_QUIRK_BROKEN_CACHE_FLUSH),



	/*

	 * Kingston EMMC04G-M627 advertises TRIM but it does not seems to

drivers/mmc/host/sdhci-pci-gli.c

+16 −0
Original line number Diff line number Diff line
@@ -28,6 +28,9 @@ 
#define PCI_GLI_9750_PM_CTRL	0xFC

#define   PCI_GLI_9750_PM_STATE	  GENMASK(1, 0)



#define PCI_GLI_9750_CORRERR_MASK				0x214

#define   PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT	  BIT(12)



#define SDHCI_GLI_9750_CFG2          0x848

#define   SDHCI_GLI_9750_CFG2_L1DLY    GENMASK(28, 24)

#define   GLI_9750_CFG2_L1DLY_VALUE    0x1F
@@ -152,6 +155,9 @@ 
#define PCI_GLI_9755_PM_CTRL     0xFC

#define   PCI_GLI_9755_PM_STATE    GENMASK(1, 0)



#define PCI_GLI_9755_CORRERR_MASK				0x214

#define   PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT	  BIT(12)



#define SDHCI_GLI_9767_GM_BURST_SIZE			0x510

#define   SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET	  BIT(8)
@@ -561,6 +567,11 @@ static void gl9750_hw_setting(struct sdhci_host *host) 
	value &= ~PCI_GLI_9750_PM_STATE;

	pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);



	/* mask the replay timer timeout of AER */

	pci_read_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, &value);

	value |= PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT;

	pci_write_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, value);



	gl9750_wt_off(host);

}
@@ -770,6 +781,11 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot) 
	value &= ~PCI_GLI_9755_PM_STATE;

	pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);



	/* mask the replay timer timeout of AER */

	pci_read_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, &value);

	value |= PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT;

	pci_write_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, value);



	gl9755_wt_off(pdev);

}