Commit b46012a2 authored by Michal Swiatkowski's avatar Michal Swiatkowski Committed by Tony Nguyen
Browse files

i40e: use libie adminq descriptors 



Use libie_aq_desc instead of i40e_aq_desc. Do needed changes to allow
clean build.

Get version descriptor is a little less detailed on i40e. To not mess up
with shifting or union inside libie desc use get version descriptor from
i40e.

Move additional caps for i40e to libie.

Fix RCT in declaration that is using libie_aq_desc;

Use libie_aq_raw() wherever it can be used.

The libie aq error is extended, cover it in ice driver just to clean
build. In next patches the libie code for that will be used in each
of intel driver.

Reviewed-by: default avatarPrzemek Kitszel <przemyslaw.kitszel@intel.com>
Signed-off-by: default avatarMichal Swiatkowski <michal.swiatkowski@linux.intel.com>
Tested-by: Rinitha S <sx.rinitha@intel.com> (A Contingent worker at Intel)
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
parent 5b36bef4

drivers/net/ethernet/intel/i40e/i40e_adminq.c

+34 −34
Original line number Diff line number Diff line
@@ -18,7 +18,7 @@ static int i40e_alloc_adminq_asq_ring(struct i40e_hw *hw) 


	ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,

					 (hw->aq.num_asq_entries *

					 sizeof(struct i40e_aq_desc)),

					 sizeof(struct libie_aq_desc)),

					 I40E_ADMINQ_DESC_ALIGNMENT);

	if (ret_code)

		return ret_code;
@@ -44,7 +44,7 @@ static int i40e_alloc_adminq_arq_ring(struct i40e_hw *hw) 


	ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,

					 (hw->aq.num_arq_entries *

					 sizeof(struct i40e_aq_desc)),

					 sizeof(struct libie_aq_desc)),

					 I40E_ADMINQ_DESC_ALIGNMENT);



	return ret_code;
@@ -80,7 +80,7 @@ static void i40e_free_adminq_arq(struct i40e_hw *hw) 
 **/

static int i40e_alloc_arq_bufs(struct i40e_hw *hw)

{

	struct i40e_aq_desc *desc;

	struct libie_aq_desc *desc;

	struct i40e_dma_mem *bi;

	int ret_code;

	int i;
@@ -108,9 +108,9 @@ static int i40e_alloc_arq_bufs(struct i40e_hw *hw) 
		/* now configure the descriptors for use */

		desc = I40E_ADMINQ_DESC(hw->aq.arq, i);



		desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);

		desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_BUF);

		if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)

			desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);

			desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_LB);

		desc->opcode = 0;

		/* This is in accordance with Admin queue design, there is no

		 * register for buffer size configuration
@@ -119,12 +119,12 @@ static int i40e_alloc_arq_bufs(struct i40e_hw *hw) 
		desc->retval = 0;

		desc->cookie_high = 0;

		desc->cookie_low = 0;

		desc->params.external.addr_high =

		desc->params.generic.addr_high =

			cpu_to_le32(upper_32_bits(bi->pa));

		desc->params.external.addr_low =

		desc->params.generic.addr_low =

			cpu_to_le32(lower_32_bits(bi->pa));

		desc->params.external.param0 = 0;

		desc->params.external.param1 = 0;

		desc->params.generic.param0 = 0;

		desc->params.generic.param1 = 0;

	}



alloc_arq_bufs:
@@ -691,8 +691,8 @@ static u16 i40e_clean_asq(struct i40e_hw *hw) 
	struct i40e_adminq_ring *asq = &(hw->aq.asq);

	struct i40e_asq_cmd_details *details;

	u16 ntc = asq->next_to_clean;

	struct i40e_aq_desc desc_cb;

	struct i40e_aq_desc *desc;

	struct libie_aq_desc desc_cb;

	struct libie_aq_desc *desc;



	desc = I40E_ADMINQ_DESC(*asq, ntc);

	details = I40E_ADMINQ_DETAILS(*asq, ntc);
@@ -750,7 +750,7 @@ static bool i40e_asq_done(struct i40e_hw *hw) 
 **/

static int

i40e_asq_send_command_atomic_exec(struct i40e_hw *hw,

				  struct i40e_aq_desc *desc,

				  struct libie_aq_desc *desc,

				  void *buff, /* can be NULL */

				  u16  buff_size,

				  struct i40e_asq_cmd_details *cmd_details,
@@ -758,7 +758,7 @@ i40e_asq_send_command_atomic_exec(struct i40e_hw *hw, 
{

	struct i40e_dma_mem *dma_buff = NULL;

	struct i40e_asq_cmd_details *details;

	struct i40e_aq_desc *desc_on_ring;

	struct libie_aq_desc *desc_on_ring;

	bool cmd_completed = false;

	u16  retval = 0;

	int status = 0;
@@ -771,7 +771,7 @@ i40e_asq_send_command_atomic_exec(struct i40e_hw *hw, 
		goto asq_send_command_error;

	}



	hw->aq.asq_last_status = I40E_AQ_RC_OK;

	hw->aq.asq_last_status = LIBIE_AQ_RC_OK;



	val = rd32(hw, I40E_PF_ATQH);

	if (val >= hw->aq.num_asq_entries) {
@@ -851,9 +851,9 @@ i40e_asq_send_command_atomic_exec(struct i40e_hw *hw, 
		/* Update the address values in the desc with the pa value

		 * for respective buffer

		 */

		desc_on_ring->params.external.addr_high =

		desc_on_ring->params.generic.addr_high =

				cpu_to_le32(upper_32_bits(dma_buff->pa));

		desc_on_ring->params.external.addr_low =

		desc_on_ring->params.generic.addr_low =

				cpu_to_le32(lower_32_bits(dma_buff->pa));

	}
@@ -905,13 +905,13 @@ i40e_asq_send_command_atomic_exec(struct i40e_hw *hw, 
			retval &= 0xff;

		}

		cmd_completed = true;

		if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK)

		if ((enum libie_aq_err)retval == LIBIE_AQ_RC_OK)

			status = 0;

		else if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_EBUSY)

		else if ((enum libie_aq_err)retval == LIBIE_AQ_RC_EBUSY)

			status = -EBUSY;

		else

			status = -EIO;

		hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;

		hw->aq.asq_last_status = (enum libie_aq_err)retval;

	}



	i40e_debug(hw, I40E_DEBUG_AQ_COMMAND,
@@ -954,7 +954,7 @@ i40e_asq_send_command_atomic_exec(struct i40e_hw *hw, 
 **/

int

i40e_asq_send_command_atomic(struct i40e_hw *hw,

			     struct i40e_aq_desc *desc,

			     struct libie_aq_desc *desc,

			     void *buff, /* can be NULL */

			     u16  buff_size,

			     struct i40e_asq_cmd_details *cmd_details,
@@ -972,7 +972,7 @@ i40e_asq_send_command_atomic(struct i40e_hw *hw, 
}



int

i40e_asq_send_command(struct i40e_hw *hw, struct i40e_aq_desc *desc,

i40e_asq_send_command(struct i40e_hw *hw, struct libie_aq_desc *desc,

		      void *buff, /* can be NULL */ u16  buff_size,

		      struct i40e_asq_cmd_details *cmd_details)

{
@@ -996,12 +996,12 @@ i40e_asq_send_command(struct i40e_hw *hw, struct i40e_aq_desc *desc, 
 **/

int

i40e_asq_send_command_atomic_v2(struct i40e_hw *hw,

				struct i40e_aq_desc *desc,

				struct libie_aq_desc *desc,

				void *buff, /* can be NULL */

				u16  buff_size,

				struct i40e_asq_cmd_details *cmd_details,

				bool is_atomic_context,

				enum i40e_admin_queue_err *aq_status)

				enum libie_aq_err *aq_status)

{

	int status;
@@ -1023,13 +1023,13 @@ i40e_asq_send_command_atomic_v2(struct i40e_hw *hw, 
 *

 *  Fill the desc with default values

 **/

void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,

void i40e_fill_default_direct_cmd_desc(struct libie_aq_desc *desc,

				       u16 opcode)

{

	/* zero out the desc */

	memset((void *)desc, 0, sizeof(struct i40e_aq_desc));

	memset((void *)desc, 0, sizeof(struct libie_aq_desc));

	desc->opcode = cpu_to_le16(opcode);

	desc->flags = cpu_to_le16(I40E_AQ_FLAG_SI);

	desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_SI);

}



/**
@@ -1047,7 +1047,7 @@ int i40e_clean_arq_element(struct i40e_hw *hw, 
			   u16 *pending)

{

	u16 ntc = hw->aq.arq.next_to_clean;

	struct i40e_aq_desc *desc;

	struct libie_aq_desc *desc;

	struct i40e_dma_mem *bi;

	int ret_code = 0;

	u16 desc_idx;
@@ -1081,9 +1081,9 @@ int i40e_clean_arq_element(struct i40e_hw *hw, 
	desc_idx = ntc;



	hw->aq.arq_last_status =

		(enum i40e_admin_queue_err)le16_to_cpu(desc->retval);

		(enum libie_aq_err)le16_to_cpu(desc->retval);

	flags = le16_to_cpu(desc->flags);

	if (flags & I40E_AQ_FLAG_ERR) {

	if (flags & LIBIE_AQ_FLAG_ERR) {

		ret_code = -EIO;

		i40e_debug(hw,

			   I40E_DEBUG_AQ_MESSAGE,
@@ -1107,14 +1107,14 @@ int i40e_clean_arq_element(struct i40e_hw *hw, 
	 * size

	 */

	bi = &hw->aq.arq.r.arq_bi[ntc];

	memset((void *)desc, 0, sizeof(struct i40e_aq_desc));

	memset((void *)desc, 0, sizeof(struct libie_aq_desc));



	desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);

	desc->flags = cpu_to_le16(LIBIE_AQ_FLAG_BUF);

	if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)

		desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);

		desc->flags |= cpu_to_le16(LIBIE_AQ_FLAG_LB);

	desc->datalen = cpu_to_le16((u16)bi->size);

	desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa));

	desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa));

	desc->params.generic.addr_high = cpu_to_le32(upper_32_bits(bi->pa));

	desc->params.generic.addr_low = cpu_to_le32(lower_32_bits(bi->pa));



	/* set tail = the last cleaned desc index. */

	wr32(hw, I40E_PF_ARQT, ntc);

drivers/net/ethernet/intel/i40e/i40e_adminq.h

+6 −6
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ 
#include "i40e_adminq_cmd.h"



#define I40E_ADMINQ_DESC(R, i)   \

	(&(((struct i40e_aq_desc *)((R).desc_buf.va))[i]))

	(&(((struct libie_aq_desc *)((R).desc_buf.va))[i]))



#define I40E_ADMINQ_DESC_ALIGNMENT 4096
@@ -39,7 +39,7 @@ struct i40e_asq_cmd_details { 
	u16 flags_dis;

	bool async;

	bool postpone;

	struct i40e_aq_desc *wb_desc;

	struct libie_aq_desc *wb_desc;

};



#define I40E_ADMINQ_DETAILS(R, i)   \
@@ -47,7 +47,7 @@ struct i40e_asq_cmd_details { 


/* ARQ event information */

struct i40e_arq_event_info {

	struct i40e_aq_desc desc;

	struct libie_aq_desc desc;

	u16 msg_len;

	u16 buf_len;

	u8 *msg_buf;
@@ -72,8 +72,8 @@ struct i40e_adminq_info { 
	struct mutex arq_mutex; /* Receive queue lock */



	/* last status values on send and receive queues */

	enum i40e_admin_queue_err asq_last_status;

	enum i40e_admin_queue_err arq_last_status;

	enum libie_aq_err asq_last_status;

	enum libie_aq_err arq_last_status;

};



/**
@@ -119,7 +119,7 @@ static inline int i40e_aq_rc_to_posix(int aq_ret, int aq_rc) 
#define I40E_AQ_LARGE_BUF	512

#define I40E_ASQ_CMD_TIMEOUT	250000  /* usecs */



void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,

void i40e_fill_default_direct_cmd_desc(struct libie_aq_desc *desc,

				       u16 opcode);



#endif /* _I40E_ADMINQ_H_ */

drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h

+2 −153
Original line number Diff line number Diff line
@@ -4,6 +4,8 @@ 
#ifndef _I40E_ADMINQ_CMD_H_

#define _I40E_ADMINQ_CMD_H_



#include <linux/net/intel/libie/adminq.h>



#include <linux/bits.h>

#include <linux/types.h>
@@ -30,75 +32,6 @@ 
/* API version 1.10 for X722 devices adds ability to request FEC encoding */

#define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A



struct i40e_aq_desc {

	__le16 flags;

	__le16 opcode;

	__le16 datalen;

	__le16 retval;

	__le32 cookie_high;

	__le32 cookie_low;

	union {

		struct {

			__le32 param0;

			__le32 param1;

			__le32 param2;

			__le32 param3;

		} internal;

		struct {

			__le32 param0;

			__le32 param1;

			__le32 addr_high;

			__le32 addr_low;

		} external;

		u8 raw[16];

	} params;

};



/* Flags sub-structure

 * |0  |1  |2  |3  |4  |5  |6  |7  |8  |9  |10 |11 |12 |13 |14 |15 |

 * |DD |CMP|ERR|VFE| * *  RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |

 */



/* command flags and offsets*/

#define I40E_AQ_FLAG_ERR_SHIFT	2

#define I40E_AQ_FLAG_LB_SHIFT	9

#define I40E_AQ_FLAG_RD_SHIFT	10

#define I40E_AQ_FLAG_BUF_SHIFT	12

#define I40E_AQ_FLAG_SI_SHIFT	13



#define I40E_AQ_FLAG_ERR	BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4    */

#define I40E_AQ_FLAG_LB		BIT(I40E_AQ_FLAG_LB_SHIFT)  /* 0x200  */

#define I40E_AQ_FLAG_RD		BIT(I40E_AQ_FLAG_RD_SHIFT)  /* 0x400  */

#define I40E_AQ_FLAG_BUF	BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */

#define I40E_AQ_FLAG_SI		BIT(I40E_AQ_FLAG_SI_SHIFT)  /* 0x2000 */



/* error codes */

enum i40e_admin_queue_err {

	I40E_AQ_RC_OK		= 0,  /* success */

	I40E_AQ_RC_EPERM	= 1,  /* Operation not permitted */

	I40E_AQ_RC_ENOENT	= 2,  /* No such element */

	I40E_AQ_RC_ESRCH	= 3,  /* Bad opcode */

	I40E_AQ_RC_EINTR	= 4,  /* operation interrupted */

	I40E_AQ_RC_EIO		= 5,  /* I/O error */

	I40E_AQ_RC_ENXIO	= 6,  /* No such resource */

	I40E_AQ_RC_E2BIG	= 7,  /* Arg too long */

	I40E_AQ_RC_EAGAIN	= 8,  /* Try again */

	I40E_AQ_RC_ENOMEM	= 9,  /* Out of memory */

	I40E_AQ_RC_EACCES	= 10, /* Permission denied */

	I40E_AQ_RC_EFAULT	= 11, /* Bad address */

	I40E_AQ_RC_EBUSY	= 12, /* Device or resource busy */

	I40E_AQ_RC_EEXIST	= 13, /* object already exists */

	I40E_AQ_RC_EINVAL	= 14, /* Invalid argument */

	I40E_AQ_RC_ENOTTY	= 15, /* Not a typewriter */

	I40E_AQ_RC_ENOSPC	= 16, /* No space left or alloc failure */

	I40E_AQ_RC_ENOSYS	= 17, /* Function not implemented */

	I40E_AQ_RC_ERANGE	= 18, /* Parameter out of range */

	I40E_AQ_RC_EFLUSHED	= 19, /* Cmd flushed due to prev cmd error */

	I40E_AQ_RC_BAD_ADDR	= 20, /* Descriptor contains a bad pointer */

	I40E_AQ_RC_EMODE	= 21, /* Op not allowed in current dev mode */

	I40E_AQ_RC_EFBIG	= 22, /* File too large */

};



/* Admin Queue command opcodes */

enum i40e_admin_queue_opc {

	/* aq commands */
@@ -320,21 +253,6 @@ struct i40e_aqc_get_version { 
	__le16 api_minor;

};



I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);



/* Send driver version (indirect 0x0002) */

struct i40e_aqc_driver_version {

	u8	driver_major_ver;

	u8	driver_minor_ver;

	u8	driver_build_ver;

	u8	driver_subbuild_ver;

	u8	reserved[4];

	__le32	address_high;

	__le32	address_low;

};



I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);



/* Queue Shutdown (direct 0x0003) */

struct i40e_aqc_queue_shutdown {

	__le32	driver_unloading;
@@ -352,75 +270,6 @@ struct i40e_aqc_set_pf_context { 


I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);



/* Request resource ownership (direct 0x0008)

 * Release resource ownership (direct 0x0009)

 */

struct i40e_aqc_request_resource {

	__le16	resource_id;

	__le16	access_type;

	__le32	timeout;

	__le32	resource_number;

	u8	reserved[4];

};



I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);



/* Get function capabilities (indirect 0x000A)

 * Get device capabilities (indirect 0x000B)

 */

struct i40e_aqc_list_capabilites {

	u8 command_flags;

	u8 pf_index;

	u8 reserved[2];

	__le32 count;

	__le32 addr_high;

	__le32 addr_low;

};



I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);



struct i40e_aqc_list_capabilities_element_resp {

	__le16	id;

	u8	major_rev;

	u8	minor_rev;

	__le32	number;

	__le32	logical_id;

	__le32	phys_id;

	u8	reserved[16];

};



/* list of caps */



#define I40E_AQ_CAP_ID_SWITCH_MODE	0x0001

#define I40E_AQ_CAP_ID_MNG_MODE		0x0002

#define I40E_AQ_CAP_ID_NPAR_ACTIVE	0x0003

#define I40E_AQ_CAP_ID_OS2BMC_CAP	0x0004

#define I40E_AQ_CAP_ID_FUNCTIONS_VALID	0x0005

#define I40E_AQ_CAP_ID_SRIOV		0x0012

#define I40E_AQ_CAP_ID_VF		0x0013

#define I40E_AQ_CAP_ID_VMDQ		0x0014

#define I40E_AQ_CAP_ID_8021QBG		0x0015

#define I40E_AQ_CAP_ID_8021QBR		0x0016

#define I40E_AQ_CAP_ID_VSI		0x0017

#define I40E_AQ_CAP_ID_DCB		0x0018

#define I40E_AQ_CAP_ID_FCOE		0x0021

#define I40E_AQ_CAP_ID_ISCSI		0x0022

#define I40E_AQ_CAP_ID_RSS		0x0040

#define I40E_AQ_CAP_ID_RXQ		0x0041

#define I40E_AQ_CAP_ID_TXQ		0x0042

#define I40E_AQ_CAP_ID_MSIX		0x0043

#define I40E_AQ_CAP_ID_VF_MSIX		0x0044

#define I40E_AQ_CAP_ID_FLOW_DIRECTOR	0x0045

#define I40E_AQ_CAP_ID_1588		0x0046

#define I40E_AQ_CAP_ID_IWARP		0x0051

#define I40E_AQ_CAP_ID_LED		0x0061

#define I40E_AQ_CAP_ID_SDP		0x0062

#define I40E_AQ_CAP_ID_MDIO		0x0063

#define I40E_AQ_CAP_ID_WSR_PROT		0x0064

#define I40E_AQ_CAP_ID_NVM_MGMT		0x0080

#define I40E_AQ_CAP_ID_FLEX10		0x00F1

#define I40E_AQ_CAP_ID_CEM		0x00F2



/* Set CPPM Configuration (direct 0x0103) */

struct i40e_aqc_cppm_configuration {

	__le16	command_flags;

drivers/net/ethernet/intel/i40e/i40e_common.c

+368 −386

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/intel/i40e/i40e_dcb.c

+5 −5
Original line number Diff line number Diff line
@@ -750,7 +750,7 @@ static int i40e_get_ieee_dcb_config(struct i40e_hw *hw) 
				     I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,

				     &hw->remote_dcbx_config);

	/* Don't treat ENOENT as an error for Remote MIBs */

	if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT)

	if (hw->aq.asq_last_status == LIBIE_AQ_RC_ENOENT)

		ret = 0;



out:
@@ -799,7 +799,7 @@ int i40e_get_dcb_config(struct i40e_hw *hw) 
	}



	/* CEE mode not enabled try querying IEEE data */

	if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT)

	if (hw->aq.asq_last_status == LIBIE_AQ_RC_ENOENT)

		return i40e_get_ieee_dcb_config(hw);



	if (ret)
@@ -816,7 +816,7 @@ int i40e_get_dcb_config(struct i40e_hw *hw) 
				     I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,

				     &hw->remote_dcbx_config);

	/* Don't treat ENOENT as an error for Remote MIBs */

	if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT)

	if (hw->aq.asq_last_status == LIBIE_AQ_RC_ENOENT)

		ret = 0;



out:
@@ -925,11 +925,11 @@ i40e_get_fw_lldp_status(struct i40e_hw *hw, 


	if (!ret) {

		*lldp_status = I40E_GET_FW_LLDP_STATUS_ENABLED;

	} else if (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT) {

	} else if (hw->aq.asq_last_status == LIBIE_AQ_RC_ENOENT) {

		/* MIB is not available yet but the agent is running */

		*lldp_status = I40E_GET_FW_LLDP_STATUS_ENABLED;

		ret = 0;

	} else if (hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {

	} else if (hw->aq.asq_last_status == LIBIE_AQ_RC_EPERM) {

		*lldp_status = I40E_GET_FW_LLDP_STATUS_DISABLED;

		ret = 0;

	}