Commit b4abe06d authored by Brian Nguyen's avatar Brian Nguyen Committed by Matthew Brost
Browse files

drm/xe/xe_tlb_inval: Modify fence interface to support PPC flush 



Allow tlb_invalidation to control when driver wants to flush the
Private Physical Cache (PPC) as a process of the tlb invalidation
process.

Default behavior is still to always flush the PPC but driver now has the
option to disable it.

v2:
 - Revise commit/kernel doc descriptions. (Shuicheng)
 - Remove unused function. (Shuicheng)
 - Remove bool flush_cache parameter from fence,
   and various function inputs. (Matthew B)

Signed-off-by: default avatarBrian Nguyen <brian3.nguyen@intel.com>
Reviewed-by: default avatarMatthew Brost <matthew.brost@intel.com>
Reviewed-by: default avatarTejas Upadhyay <tejas.upadhyay@intel.com>
Cc: Shuicheng Lin <shuicheng.lin@intel.com>
Signed-off-by: default avatarMatthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20251212213225.3564537-14-brian3.nguyen@intel.com
parent 44ece225

drivers/gpu/drm/xe/xe_guc_tlb_inval.c

+6 −3
Original line number Diff line number Diff line
@@ -34,9 +34,12 @@ static int send_tlb_inval(struct xe_guc *guc, const u32 *action, int len) 
			      G2H_LEN_DW_TLB_INVALIDATE, 1);

}



#define MAKE_INVAL_OP(type)	((type << XE_GUC_TLB_INVAL_TYPE_SHIFT) | \

#define MAKE_INVAL_OP_FLUSH(type, flush_cache)	((type << XE_GUC_TLB_INVAL_TYPE_SHIFT) | \

		XE_GUC_TLB_INVAL_MODE_HEAVY << XE_GUC_TLB_INVAL_MODE_SHIFT | \

		XE_GUC_TLB_INVAL_FLUSH_CACHE)

		(flush_cache ? \

		XE_GUC_TLB_INVAL_FLUSH_CACHE : 0))



#define MAKE_INVAL_OP(type)	MAKE_INVAL_OP_FLUSH(type, true)



static int send_tlb_inval_all(struct xe_tlb_inval *tlb_inval, u32 seqno)

{
@@ -152,7 +155,7 @@ static int send_tlb_inval_ppgtt(struct xe_tlb_inval *tlb_inval, u32 seqno, 
						    ilog2(SZ_2M) + 1)));

		xe_gt_assert(gt, IS_ALIGNED(start, length));



		action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_PAGE_SELECTIVE);

		action[len++] = MAKE_INVAL_OP_FLUSH(XE_GUC_TLB_INVAL_PAGE_SELECTIVE, true);

		action[len++] = asid;

		action[len++] = lower_32_bits(start);

		action[len++] = upper_32_bits(start);