Commit b4db7971 authored by Ovidiu Bunea's avatar Ovidiu Bunea Committed by Alex Deucher
Browse files

drm/amd/display: Update IPS sequential_ono requirement checks 



[why & how]
ASICs that require special RCG/PG programming are determined based
on hw_internal_rev. Update these checks to properly include all such
ASICs.

Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarOvidiu Bunea <Ovidiu.Bunea@amd.com>
Signed-off-by: default avatarRay Wu <ray.wu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent da072da2

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

+1 −1
Original line number Diff line number Diff line
@@ -138,7 +138,7 @@ bool dpp35_construct( 
	dpp->base.funcs = &dcn35_dpp_funcs;



	// w/a for cursor memory stuck in LS by programming DISPCLK_R_GATE_DISABLE, limit w/a to some ASIC revs

	if (dpp->base.ctx->asic_id.hw_internal_rev <= 0x10)

	if (dpp->base.ctx->asic_id.hw_internal_rev < 0x40)

		dpp->dispclk_r_gate_disable = true;

	return ret;

}

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -1903,7 +1903,7 @@ static bool dcn35_resource_construct( 
	dc->caps.max_disp_clock_khz_at_vmin = 650000;



	/* Sequential ONO is based on ASIC. */

	if (dc->ctx->asic_id.hw_internal_rev > 0x10)

	if (dc->ctx->asic_id.hw_internal_rev >= 0x40)

		dc->caps.sequential_ono = true;



	/* Use pipe context based otg sync logic */

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -1876,7 +1876,7 @@ static bool dcn36_resource_construct( 
	dc->caps.max_disp_clock_khz_at_vmin = 650000;



	/* Sequential ONO is based on ASIC. */

	if (dc->ctx->asic_id.hw_internal_rev > 0x10)

	if (dc->ctx->asic_id.hw_internal_rev >= 0x40)

		dc->caps.sequential_ono = true;



	/* Use pipe context based otg sync logic */