Commit b51adc77 authored by Rohit Visavalia's avatar Rohit Visavalia Committed by Stephen Boyd
Browse files

dt-bindings: clock: xilinx: Convert VCU bindings to dtschema 



Convert AMD (Xilinx) VCU bindings to yaml format.
Additional changes:
   - move xlnx_vcu DT binding to clock from soc following commit
     a2fe7baa ("clk: xilinx: move xlnx_vcu clock driver from soc")
   - corrected clock sequence as per xilinx device-tree generator

Signed-off-by: default avatarRohit Visavalia <rohit.visavalia@xilinx.com>
Link: https://lore.kernel.org/r/20250107044038.100945-2-rohit.visavalia@amd.com


Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 40384c84

Documentation/devicetree/bindings/clock/xlnx,vcu.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/xlnx,vcu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LogicoreIP designed compatible with Xilinx ZYNQ family.



maintainers:

  - Rohit Visavalia <rohit.visavalia@amd.com>



description:

  LogicoreIP design to provide the isolation between processing system

  and programmable logic. Also provides the list of register set to configure

  the frequency.



properties:

  compatible:

    items:

      - enum:

          - xlnx,vcu

          - xlnx,vcu-logicoreip-1.0



  reg:

    maxItems: 1



  clocks:

    items:

      - description: pll ref clocksource

      - description: aclk



  clock-names:

    items:

      - const: pll_ref

      - const: aclk



required:

  - reg

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/gpio/gpio.h>

    fpga {

        #address-cells = <2>;

        #size-cells = <2>;

        xlnx_vcu: vcu@a0040000 {

            compatible = "xlnx,vcu-logicoreip-1.0";

            reg = <0x0 0xa0040000 0x0 0x1000>;

            clocks = <&si570_1>, <&clkc 71>;

            clock-names = "pll_ref", "aclk";

        };

    };

Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt

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LogicoreIP designed compatible with Xilinx ZYNQ family.

-------------------------------------------------------



General concept

---------------



LogicoreIP design to provide the isolation between processing system

and programmable logic. Also provides the list of register set to configure

the frequency.



Required properties:

- compatible: shall be one of:

	"xlnx,vcu"

	"xlnx,vcu-logicoreip-1.0"

- reg : The base offset and size of the VCU_PL_SLCR register space.

- clocks: phandle for aclk and pll_ref clocksource

- clock-names: The identification string, "aclk", is always required for

   the axi clock. "pll_ref" is required for pll.

Example:



	xlnx_vcu: vcu@a0040000 {

		compatible = "xlnx,vcu-logicoreip-1.0";

		reg = <0x0 0xa0040000 0x0 0x1000>;

		clocks = <&si570_1>, <&clkc 71>;

		clock-names = "pll_ref", "aclk";

	};