Commit b522c8af authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Update skylake/skylakex events/metrics 

Update skylake events to v60 and skylakex events to v1.30, adding the
events FP_ARITH_INST_RETIRED.4_FLOPS, FP_ARITH_INST_RETIRED.8_FLOPS,
FP_ARITH_INST_RETIRED.SCALAR, FP_ARITH_INST_RETIRED.VECTOR and
INT_MISC.CLEARS_COUNT. Metrics are updated to make TMA info metric
names synchronized. Events and metrics were generated by:
https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py



Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Richter <tmricht@linux.ibm.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20230517173805.602113-12-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 9a5511ea

tools/perf/pmu-events/arch/x86/mapfile.csv

+2 −2
Original line number Diff line number Diff line
@@ -26,8 +26,8 @@ GenuineIntel-6-2A,v19,sandybridge,core 
GenuineIntel-6-(8F|CF),v1.13,sapphirerapids,core

GenuineIntel-6-AF,v1.00,sierraforest,core

GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core

GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v55,skylake,core

GenuineIntel-6-55-[01234],v1.29,skylakex,core

GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v56,skylake,core

GenuineIntel-6-55-[01234],v1.30,skylakex,core

GenuineIntel-6-86,v1.20,snowridgex,core

GenuineIntel-6-8[CD],v1.10,tigerlake,core

GenuineIntel-6-2C,v4,westmereep-dp,core

tools/perf/pmu-events/arch/x86/skylake/floating-point.json

+8 −0
Original line number Diff line number Diff line
@@ -31,6 +31,14 @@ 
        "SampleAfterValue": "2000003",

        "UMask": "0x20"

    },

    {

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",

        "EventCode": "0xC7",

        "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",

        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision  floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "1000003",

        "UMask": "0x18"

    },

    {

        "BriefDescription": "Counts once for most SIMD scalar computational floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",

        "EventCode": "0xC7",

tools/perf/pmu-events/arch/x86/skylake/pipeline.json

+12 −3
Original line number Diff line number Diff line
@@ -26,12 +26,21 @@ 
        "UMask": "0x4"

    },

    {

        "BriefDescription": "Conditional branch instructions retired.",

        "BriefDescription": "Conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.CONDITIONAL]",

        "Errata": "SKL091",

        "EventCode": "0xC4",

        "EventName": "BR_INST_RETIRED.COND",

        "PublicDescription": "This event counts conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.CONDITIONAL]",

        "SampleAfterValue": "400009",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.COND]",

        "Errata": "SKL091",

        "EventCode": "0xC4",

        "EventName": "BR_INST_RETIRED.CONDITIONAL",

        "PEBS": "1",

        "PublicDescription": "This event counts conditional branch instructions retired.",

        "PublicDescription": "This event counts conditional branch instructions retired. [This event is alias to BR_INST_RETIRED.COND]",

        "SampleAfterValue": "400009",

        "UMask": "0x1"

    },
@@ -405,9 +414,9 @@ 
        "UMask": "0x1"

    },

    {

        "AnyThread": "1",

        "BriefDescription": "Clears speculative count",

        "CounterMask": "1",

        "EdgeDetect": "1",

        "EventCode": "0x0D",

        "EventName": "INT_MISC.CLEARS_COUNT",

        "PublicDescription": "Counts the number of speculative clears due to any type of branch misprediction or machine clears",

tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json

+437 −438

File changed.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/x86/skylakex/floating-point.json

+31 −0
Original line number Diff line number Diff line
@@ -31,6 +31,14 @@ 
        "SampleAfterValue": "2000003",

        "UMask": "0x20"

    },

    {

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",

        "EventCode": "0xC7",

        "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",

        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision  floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "1000003",

        "UMask": "0x18"

    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "EventCode": "0xC7",
@@ -47,6 +55,22 @@ 
        "SampleAfterValue": "2000003",

        "UMask": "0x80"

    },

    {

        "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision  FP instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",

        "EventCode": "0xC7",

        "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS",

        "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision  floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "1000003",

        "UMask": "0x18"

    },

    {

        "BriefDescription": "Counts once for most SIMD scalar computational floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",

        "EventCode": "0xC7",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR",

        "PublicDescription": "Counts once for most SIMD scalar computational single precision and double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "2000003",

        "UMask": "0x3"

    },

    {

        "BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",

        "EventCode": "0xC7",
@@ -63,6 +87,13 @@ 
        "SampleAfterValue": "2000003",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "Number of any Vector retired FP arithmetic instructions",

        "EventCode": "0xC7",

        "EventName": "FP_ARITH_INST_RETIRED.VECTOR",

        "SampleAfterValue": "2000003",

        "UMask": "0xfc"

    },

    {

        "BriefDescription": "Cycles with any input/output SSE or FP assist",

        "CounterMask": "1",