Commit b555d191 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'perf-tools-fixes-for-v6.8-1-2024-02-01' of... 

Merge tag 'perf-tools-fixes-for-v6.8-1-2024-02-01' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools

Pull perf tools fixes from Arnaldo Carvalho de Melo:
 "Vendor events:

   - Intel Alderlake/Sapphire Rapids metric fixes, the CPU type
     ("cpu_atom", "cpu_core") needs to be used as a prefix to be
     considered on a metric formula, detected via one of the 'perf test'
     entries.

  'perf test' fixes:

   - Fix the creation of event selector lists on 'perf test' entries, by
     initializing the sample ID flag, which is done by 'perf record', so
     this fix affects only the tests, the common case isn't affected

   - Make 'perf list' respect debug settings (-v) to fix its 'perf test'
     entry

   - Fix 'perf script' test when python support isn't enabled

   - Special case 'perf script' tests on s390, where only DWARF call
     graphs are supported and only on software events

   - Make 'perf daemon' signal test less racy

  Compiler warnings/errors:

   - Remove needless malloc(0) call in 'perf top' that triggers
     -Walloc-size

   - Fix calloc() argument order to address error introduced in gcc-14

  Build:

   - Make minimal shellcheck version to v0.6.0, avoiding the build to
     fail with older versions

  Sync kernel header copies:

   - stat.h to pick STATX_MNT_ID_UNIQUE

   - msr-index.h to pick IA32_MKTME_KEYID_PARTITIONING

   - drm.h to pick DRM_IOCTL_MODE_CLOSEFB

   - unistd.h to pick {list,stat}mount,
     lsm_{[gs]et_self_attr,list_modules} syscall numbers

   - x86 cpufeatures to pick TDX, Zen, APIC MSR fence changes

   - x86's mem{cpy,set}_64.S used in 'perf bench'

   - Also, without tooling effects: asm-generic/unaligned.h, mount.h,
     fcntl.h, kvm headers"

* tag 'perf-tools-fixes-for-v6.8-1-2024-02-01' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools: (21 commits)
  perf tools headers: update the asm-generic/unaligned.h copy with the kernel sources
  tools include UAPI: Sync linux/mount.h copy with the kernel sources
  perf evlist: Fix evlist__new_default() for > 1 core PMU
  tools headers: Update the copy of x86's mem{cpy,set}_64.S used in 'perf bench'
  tools headers x86 cpufeatures: Sync with the kernel sources to pick TDX, Zen, APIC MSR fence changes
  tools headers UAPI: Sync unistd.h to pick {list,stat}mount, lsm_{[gs]et_self_attr,list_modules} syscall numbers
  perf vendor events intel: Alderlake/sapphirerapids metric fixes
  tools headers UAPI: Sync kvm headers with the kernel sources
  perf tools: Fix calloc() arguments to address error introduced in gcc-14
  perf top: Remove needless malloc(0) call that triggers -Walloc-size
  perf build: Make minimal shellcheck version to v0.6.0
  tools headers UAPI: Update tools's copy of drm.h headers to pick DRM_IOCTL_MODE_CLOSEFB
  perf test shell daemon: Make signal test less racy
  perf test shell script: Fix test for python being disabled
  perf test: Workaround debug output in list test
  perf list: Add output file option
  perf list: Switch error message to pr_err() to respect debug settings (-v)
  perf test: Fix 'perf script' tests on s390
  tools headers UAPI: Sync linux/fcntl.h with the kernel sources
  tools arch x86: Sync the msr-index.h copy with the kernel sources to pick IA32_MKTME_KEYID_PARTITIONING
  ...
parents 56897d51 fdd0ae72

tools/arch/x86/include/asm/cpufeatures.h

+7 −1
Original line number Diff line number Diff line
@@ -198,6 +198,7 @@ 
#define X86_FEATURE_CAT_L3		( 7*32+ 4) /* Cache Allocation Technology L3 */

#define X86_FEATURE_CAT_L2		( 7*32+ 5) /* Cache Allocation Technology L2 */

#define X86_FEATURE_CDP_L3		( 7*32+ 6) /* Code and Data Prioritization L3 */

#define X86_FEATURE_TDX_HOST_PLATFORM	( 7*32+ 7) /* Platform supports being a TDX host */

#define X86_FEATURE_HW_PSTATE		( 7*32+ 8) /* AMD HW-PState */

#define X86_FEATURE_PROC_FEEDBACK	( 7*32+ 9) /* AMD ProcFeedbackInterface */

#define X86_FEATURE_XCOMPACTED		( 7*32+10) /* "" Use compacted XSTATE (XSAVES or XSAVEC) */
@@ -308,10 +309,14 @@ 
#define X86_FEATURE_SMBA		(11*32+21) /* "" Slow Memory Bandwidth Allocation */

#define X86_FEATURE_BMEC		(11*32+22) /* "" Bandwidth Monitoring Event Configuration */

#define X86_FEATURE_USER_SHSTK		(11*32+23) /* Shadow stack support for user mode applications */



#define X86_FEATURE_SRSO		(11*32+24) /* "" AMD BTB untrain RETs */

#define X86_FEATURE_SRSO_ALIAS		(11*32+25) /* "" AMD BTB untrain RETs through aliasing */

#define X86_FEATURE_IBPB_ON_VMEXIT	(11*32+26) /* "" Issue an IBPB only on VMEXIT */

#define X86_FEATURE_APIC_MSRS_FENCE	(11*32+27) /* "" IA32_TSC_DEADLINE and X2APIC MSRs need fencing */

#define X86_FEATURE_ZEN2		(11*32+28) /* "" CPU based on Zen2 microarchitecture */

#define X86_FEATURE_ZEN3		(11*32+29) /* "" CPU based on Zen3 microarchitecture */

#define X86_FEATURE_ZEN4		(11*32+30) /* "" CPU based on Zen4 microarchitecture */

#define X86_FEATURE_ZEN1		(11*32+31) /* "" CPU based on Zen1 microarchitecture */



/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */

#define X86_FEATURE_AVX_VNNI		(12*32+ 4) /* AVX VNNI instructions */
@@ -495,6 +500,7 @@ 
#define X86_BUG_EIBRS_PBRSB		X86_BUG(28) /* EIBRS is vulnerable to Post Barrier RSB Predictions */

#define X86_BUG_SMT_RSB			X86_BUG(29) /* CPU is vulnerable to Cross-Thread Return Address Predictions */

#define X86_BUG_GDS			X86_BUG(30) /* CPU is affected by Gather Data Sampling */

#define X86_BUG_TDX_PW_MCE		X86_BUG(31) /* CPU may incur #MC if non-TD software does partial write to TDX private memory */



/* BUG word 2 */

#define X86_BUG_SRSO			X86_BUG(1*32 + 0) /* AMD SRSO bug */

tools/arch/x86/include/asm/msr-index.h

+8 −0
Original line number Diff line number Diff line
@@ -237,6 +237,11 @@ 
#define LBR_INFO_CYCLES			0xffff

#define LBR_INFO_BR_TYPE_OFFSET		56

#define LBR_INFO_BR_TYPE		(0xfull << LBR_INFO_BR_TYPE_OFFSET)

#define LBR_INFO_BR_CNTR_OFFSET		32

#define LBR_INFO_BR_CNTR_NUM		4

#define LBR_INFO_BR_CNTR_BITS		2

#define LBR_INFO_BR_CNTR_MASK		GENMASK_ULL(LBR_INFO_BR_CNTR_BITS - 1, 0)

#define LBR_INFO_BR_CNTR_FULL_MASK	GENMASK_ULL(LBR_INFO_BR_CNTR_NUM * LBR_INFO_BR_CNTR_BITS - 1, 0)



#define MSR_ARCH_LBR_CTL		0x000014ce

#define ARCH_LBR_CTL_LBREN		BIT(0)
@@ -536,6 +541,9 @@ 
#define MSR_RELOAD_PMC0			0x000014c1

#define MSR_RELOAD_FIXED_CTR0		0x00001309



/* KeyID partitioning between MKTME and TDX */

#define MSR_IA32_MKTME_KEYID_PARTITIONING	0x00000087



/*

 * AMD64 MSRs. Not complete. See the architecture manual for a more

 * complete list.

tools/arch/x86/include/uapi/asm/kvm.h

+3 −0
Original line number Diff line number Diff line
@@ -562,4 +562,7 @@ struct kvm_pmu_event_filter { 
/* x86-specific KVM_EXIT_HYPERCALL flags. */

#define KVM_EXIT_HYPERCALL_LONG_MODE	BIT(0)



#define KVM_X86_DEFAULT_VM	0

#define KVM_X86_SW_PROTECTED_VM	1



#endif /* _ASM_X86_KVM_H */

tools/arch/x86/lib/memcpy_64.S

+2 −2
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright 2002 Andi Kleen */



#include <linux/export.h>

#include <linux/linkage.h>

#include <asm/errno.h>

#include <asm/cpufeatures.h>

#include <asm/alternative.h>

#include <asm/export.h>



.section .noinstr.text, "ax"
@@ -39,7 +39,7 @@ SYM_TYPED_FUNC_START(__memcpy) 
SYM_FUNC_END(__memcpy)

EXPORT_SYMBOL(__memcpy)



SYM_FUNC_ALIAS(memcpy, __memcpy)

SYM_FUNC_ALIAS_MEMFUNC(memcpy, __memcpy)

EXPORT_SYMBOL(memcpy)



SYM_FUNC_START_LOCAL(memcpy_orig)

tools/arch/x86/lib/memset_64.S

+2 −2
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright 2002 Andi Kleen, SuSE Labs */



#include <linux/export.h>

#include <linux/linkage.h>

#include <asm/cpufeatures.h>

#include <asm/alternative.h>

#include <asm/export.h>



.section .noinstr.text, "ax"
@@ -40,7 +40,7 @@ SYM_FUNC_START(__memset) 
SYM_FUNC_END(__memset)

EXPORT_SYMBOL(__memset)



SYM_FUNC_ALIAS(memset, __memset)

SYM_FUNC_ALIAS_MEMFUNC(memset, __memset)

EXPORT_SYMBOL(memset)



SYM_FUNC_START_LOCAL(memset_orig)