Commit b58386a9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86-boot-2025-03-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 boot code updates from Ingo Molnar:

 - Memblock setup and other early boot code cleanups (Mike Rapoport)

 - Export e820_table_kexec[] to sysfs (Dave Young)

 - Baby steps of adding relocate_kernel() debugging support (David
   Woodhouse)

 - Replace open-coded parity calculation with parity8() (Kuan-Wei Chiu)

 - Move the LA57 trampoline to separate source file (Ard Biesheuvel)

 - Misc micro-optimizations (Uros Bizjak)

 - Drop obsolete E820_TYPE_RESERVED_KERN and related code (Mike
   Rapoport)

* tag 'x86-boot-2025-03-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/kexec: Add relocate_kernel() debugging support: Load a GDT
  x86/boot: Move the LA57 trampoline to separate source file
  x86/boot: Do not test if AC and ID eflags are changeable on x86_64
  x86/bootflag: Replace open-coded parity calculation with parity8()
  x86/bootflag: Micro-optimize sbf_write()
  x86/boot: Add missing has_cpuflag() prototype
  x86/kexec: Export e820_table_kexec[] to sysfs
  x86/boot: Change some static bootflag functions to bool
  x86/e820: Drop obsolete E820_TYPE_RESERVED_KERN and related code
  x86/boot: Split parsing of boot_params into the parse_boot_params() helper function
  x86/boot: Split kernel resources setup into the setup_kernel_resources() helper function
  x86/boot: Move setting of memblock parameters to e820__memblock_setup()
parents ebfb94d8 b25eb5f5

arch/x86/boot/compressed/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -98,6 +98,7 @@ ifdef CONFIG_X86_64 
	vmlinux-objs-$(CONFIG_AMD_MEM_ENCRYPT) += $(obj)/mem_encrypt.o

	vmlinux-objs-y += $(obj)/pgtable_64.o

	vmlinux-objs-$(CONFIG_AMD_MEM_ENCRYPT) += $(obj)/sev.o

	vmlinux-objs-y += $(obj)/la57toggle.o

endif



vmlinux-objs-$(CONFIG_ACPI) += $(obj)/acpi.o

arch/x86/boot/compressed/head_64.S

+0 −103
Original line number Diff line number Diff line
@@ -483,110 +483,7 @@ SYM_FUNC_START_LOCAL_NOALIGN(.Lrelocated) 
	jmp	*%rax

SYM_FUNC_END(.Lrelocated)



/*

 * This is the 32-bit trampoline that will be copied over to low memory. It

 * will be called using the ordinary 64-bit calling convention from code

 * running in 64-bit mode.

 *

 * Return address is at the top of the stack (might be above 4G).

 * The first argument (EDI) contains the address of the temporary PGD level

 * page table in 32-bit addressable memory which will be programmed into

 * register CR3.

 */

	.section ".rodata", "a", @progbits

SYM_CODE_START(trampoline_32bit_src)

	/*

	 * Preserve callee save 64-bit registers on the stack: this is

	 * necessary because the architecture does not guarantee that GPRs will

	 * retain their full 64-bit values across a 32-bit mode switch.

	 */

	pushq	%r15

	pushq	%r14

	pushq	%r13

	pushq	%r12

	pushq	%rbp

	pushq	%rbx



	/* Preserve top half of RSP in a legacy mode GPR to avoid truncation */

	movq	%rsp, %rbx

	shrq	$32, %rbx



	/* Switch to compatibility mode (CS.L = 0 CS.D = 1) via far return */

	pushq	$__KERNEL32_CS

	leaq	0f(%rip), %rax

	pushq	%rax

	lretq



	/*

	 * The 32-bit code below will do a far jump back to long mode and end

	 * up here after reconfiguring the number of paging levels. First, the

	 * stack pointer needs to be restored to its full 64-bit value before

	 * the callee save register contents can be popped from the stack.

	 */

.Lret:

	shlq	$32, %rbx

	orq	%rbx, %rsp



	/* Restore the preserved 64-bit registers */

	popq	%rbx

	popq	%rbp

	popq	%r12

	popq	%r13

	popq	%r14

	popq	%r15

	retq



	.code32

0:

	/* Disable paging */

	movl	%cr0, %eax

	btrl	$X86_CR0_PG_BIT, %eax

	movl	%eax, %cr0



	/* Point CR3 to the trampoline's new top level page table */

	movl	%edi, %cr3



	/* Set EFER.LME=1 as a precaution in case hypervsior pulls the rug */

	movl	$MSR_EFER, %ecx

	rdmsr

	btsl	$_EFER_LME, %eax

	/* Avoid writing EFER if no change was made (for TDX guest) */

	jc	1f

	wrmsr

1:

	/* Toggle CR4.LA57 */

	movl	%cr4, %eax

	btcl	$X86_CR4_LA57_BIT, %eax

	movl	%eax, %cr4



	/* Enable paging again. */

	movl	%cr0, %eax

	btsl	$X86_CR0_PG_BIT, %eax

	movl	%eax, %cr0



	/*

	 * Return to the 64-bit calling code using LJMP rather than LRET, to

	 * avoid the need for a 32-bit addressable stack. The destination

	 * address will be adjusted after the template code is copied into a

	 * 32-bit addressable buffer.

	 */

.Ljmp:	ljmpl	$__KERNEL_CS, $(.Lret - trampoline_32bit_src)

SYM_CODE_END(trampoline_32bit_src)



/*

 * This symbol is placed right after trampoline_32bit_src() so its address can

 * be used to infer the size of the trampoline code.

 */

SYM_DATA(trampoline_ljmp_imm_offset, .word  .Ljmp + 1 - trampoline_32bit_src)



	/*

         * The trampoline code has a size limit.

         * Make sure we fail to compile if the trampoline code grows

         * beyond TRAMPOLINE_32BIT_CODE_SIZE bytes.

	 */

	.org	trampoline_32bit_src + TRAMPOLINE_32BIT_CODE_SIZE



	.text

SYM_FUNC_START_LOCAL_NOALIGN(.Lno_longmode)

	/* This isn't an x86-64 CPU, so hang intentionally, we cannot continue */

1:

arch/x86/boot/compressed/la57toggle.S

0 → 100644
+112 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */



#include <linux/linkage.h>

#include <asm/segment.h>

#include <asm/boot.h>

#include <asm/msr.h>

#include <asm/processor-flags.h>

#include "pgtable.h"



/*

 * This is the 32-bit trampoline that will be copied over to low memory. It

 * will be called using the ordinary 64-bit calling convention from code

 * running in 64-bit mode.

 *

 * Return address is at the top of the stack (might be above 4G).

 * The first argument (EDI) contains the address of the temporary PGD level

 * page table in 32-bit addressable memory which will be programmed into

 * register CR3.

 */



	.section ".rodata", "a", @progbits

SYM_CODE_START(trampoline_32bit_src)

	/*

	 * Preserve callee save 64-bit registers on the stack: this is

	 * necessary because the architecture does not guarantee that GPRs will

	 * retain their full 64-bit values across a 32-bit mode switch.

	 */

	pushq	%r15

	pushq	%r14

	pushq	%r13

	pushq	%r12

	pushq	%rbp

	pushq	%rbx



	/* Preserve top half of RSP in a legacy mode GPR to avoid truncation */

	movq	%rsp, %rbx

	shrq	$32, %rbx



	/* Switch to compatibility mode (CS.L = 0 CS.D = 1) via far return */

	pushq	$__KERNEL32_CS

	leaq	0f(%rip), %rax

	pushq	%rax

	lretq



	/*

	 * The 32-bit code below will do a far jump back to long mode and end

	 * up here after reconfiguring the number of paging levels. First, the

	 * stack pointer needs to be restored to its full 64-bit value before

	 * the callee save register contents can be popped from the stack.

	 */

.Lret:

	shlq	$32, %rbx

	orq	%rbx, %rsp



	/* Restore the preserved 64-bit registers */

	popq	%rbx

	popq	%rbp

	popq	%r12

	popq	%r13

	popq	%r14

	popq	%r15

	retq



	.code32

0:

	/* Disable paging */

	movl	%cr0, %eax

	btrl	$X86_CR0_PG_BIT, %eax

	movl	%eax, %cr0



	/* Point CR3 to the trampoline's new top level page table */

	movl	%edi, %cr3



	/* Set EFER.LME=1 as a precaution in case hypervsior pulls the rug */

	movl	$MSR_EFER, %ecx

	rdmsr

	btsl	$_EFER_LME, %eax

	/* Avoid writing EFER if no change was made (for TDX guest) */

	jc	1f

	wrmsr

1:

	/* Toggle CR4.LA57 */

	movl	%cr4, %eax

	btcl	$X86_CR4_LA57_BIT, %eax

	movl	%eax, %cr4



	/* Enable paging again. */

	movl	%cr0, %eax

	btsl	$X86_CR0_PG_BIT, %eax

	movl	%eax, %cr0



	/*

	 * Return to the 64-bit calling code using LJMP rather than LRET, to

	 * avoid the need for a 32-bit addressable stack. The destination

	 * address will be adjusted after the template code is copied into a

	 * 32-bit addressable buffer.

	 */

.Ljmp:	ljmpl	$__KERNEL_CS, $(.Lret - trampoline_32bit_src)

SYM_CODE_END(trampoline_32bit_src)



/*

 * This symbol is placed right after trampoline_32bit_src() so its address can

 * be used to infer the size of the trampoline code.

 */

SYM_DATA(trampoline_ljmp_imm_offset, .word  .Ljmp + 1 - trampoline_32bit_src)



	/*

         * The trampoline code has a size limit.

         * Make sure we fail to compile if the trampoline code grows

         * beyond TRAMPOLINE_32BIT_CODE_SIZE bytes.

	 */

	.org	trampoline_32bit_src + TRAMPOLINE_32BIT_CODE_SIZE

arch/x86/boot/cpuflags.c

+9 −17
Original line number Diff line number Diff line
@@ -28,40 +28,32 @@ static int has_fpu(void) 
	return fsw == 0 && (fcw & 0x103f) == 0x003f;

}



#ifdef CONFIG_X86_32

/*

 * For building the 16-bit code we want to explicitly specify 32-bit

 * push/pop operations, rather than just saying 'pushf' or 'popf' and

 * letting the compiler choose. But this is also included from the

 * compressed/ directory where it may be 64-bit code, and thus needs

 * to be 'pushfq' or 'popfq' in that case.

 * letting the compiler choose.

 */

#ifdef __x86_64__

#define PUSHF "pushfq"

#define POPF "popfq"

#else

#define PUSHF "pushfl"

#define POPF "popfl"

#endif



int has_eflag(unsigned long mask)

bool has_eflag(unsigned long mask)

{

	unsigned long f0, f1;



	asm volatile(PUSHF "	\n\t"

		     PUSHF "	\n\t"

	asm volatile("pushfl	\n\t"

		     "pushfl	\n\t"

		     "pop %0	\n\t"

		     "mov %0,%1	\n\t"

		     "xor %2,%1	\n\t"

		     "push %1	\n\t"

		     POPF "	\n\t"

		     PUSHF "	\n\t"

		     "popfl	\n\t"

		     "pushfl	\n\t"

		     "pop %1	\n\t"

		     POPF

		     "popfl"

		     : "=&r" (f0), "=&r" (f1)

		     : "ri" (mask));



	return !!((f0^f1) & mask);

}

#endif



void cpuid_count(u32 id, u32 count, u32 *a, u32 *b, u32 *c, u32 *d)

{

arch/x86/boot/cpuflags.h

+6 −1
Original line number Diff line number Diff line
@@ -15,8 +15,13 @@ struct cpu_features { 
extern struct cpu_features cpu;

extern u32 cpu_vendor[3];



int has_eflag(unsigned long mask);

#ifdef CONFIG_X86_32

bool has_eflag(unsigned long mask);

#else

static inline bool has_eflag(unsigned long mask) { return true; }

#endif

void get_cpuflags(void);

void cpuid_count(u32 id, u32 count, u32 *a, u32 *b, u32 *c, u32 *d);

bool has_cpuflag(int flag);



#endif