Commit b5929325 authored by Martin Kaiser's avatar Martin Kaiser Committed by Greg Kroah-Hartman
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staging: r8188eu: Revert "staging: r8188eu: simplify rtw_get_ff_hwaddr"



This reverts commit fd48124e ("staging: r8188eu: simplify
rtw_get_ff_hwaddr").

The cleanup in this commit removes the qsel to addr mappings in
rtw_get_ff_hwaddr. The underlying assumption is that rtw_write_port
uses its addr parameter only for the high_queue check.

This is obviously incorrect as rtw_write_port calls
ffaddr2pipehdl(pdvobj, addr);
where addr is mapped to a usb bulk endpoint.

Unfortunately, testing did not show any problems. The Edimax V2 on which I
tested has two bulk out endpoints. I guess that with the incorrect patch,
addr could only be 0 (no high queue) or 6 (high queue), both of which were
mapped to the first bulk out endpoint. Data transfers did still work...

Fixes: fd48124e ("staging: r8188eu: simplify rtw_get_ff_hwaddr")
Signed-off-by: default avatarMartin Kaiser <martin@kaiser.cx>
Link: https://lore.kernel.org/r/20230213195407.15085-1-martin@kaiser.cx


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent c17ffe00
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+31 −1
Original line number Diff line number Diff line
@@ -1568,9 +1568,39 @@ static int rtw_br_client_tx(struct adapter *padapter, struct sk_buff **pskb)

u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe)
{
	u32 addr;
	struct pkt_attrib *pattrib = &pxmitframe->attrib;

	return pattrib->qsel == 0x11 ? HIGH_QUEUE_INX : 0;
	switch (pattrib->qsel) {
	case 0:
	case 3:
		addr = BE_QUEUE_INX;
		break;
	case 1:
	case 2:
		addr = BK_QUEUE_INX;
		break;
	case 4:
	case 5:
		addr = VI_QUEUE_INX;
		break;
	case 6:
	case 7:
		addr = VO_QUEUE_INX;
		break;
	case 0x10:
		addr = BCN_QUEUE_INX;
		break;
	case 0x11:/* BC/MC in PS (HIQ) */
		addr = HIGH_QUEUE_INX;
		break;
	case 0x12:
	default:
		addr = MGT_QUEUE_INX;
		break;
	}

	return addr;
}

/*
+7 −0
Original line number Diff line number Diff line
@@ -26,7 +26,14 @@
#define XMIT_BE_QUEUE		(2)
#define XMIT_BK_QUEUE		(3)

#define VO_QUEUE_INX		0
#define VI_QUEUE_INX		1
#define BE_QUEUE_INX		2
#define BK_QUEUE_INX		3
#define BCN_QUEUE_INX		4
#define MGT_QUEUE_INX		5
#define HIGH_QUEUE_INX		6
#define TXCMD_QUEUE_INX		7

#define HW_QUEUE_ENTRY		8