Unverified Commit b5b9e93b authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-microchip-6.19' of... 

Merge tag 'clk-microchip-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip

Pull Microchip clk driver updates from Claudiu Beznea:

 - PolarFire SoC clock driver updates to use regmaps instead of iomem
   addresses; with it, the reset control driver support for non-auxiliary
   bus probing was included as it now depends on the regmap registered
   by the clock controller driver
 - A cleanup patch for the LAN966X clk driver

* tag 'clk-microchip-6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  reset: mpfs: add non-auxiliary bus probing
  clk: lan966x: remove unused dt-bindings include
  clk: microchip: mpfs: use regmap for clocks
  dt-bindings: clk: microchip: mpfs: remove first reg region
parents 3a866087 781f60e4

Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml

+22 −14
Original line number Diff line number Diff line
@@ -22,7 +22,8 @@ properties: 
    const: microchip,mpfs-clkcfg



  reg:

    items:

    oneOf:

      - items:

          - description: |

              clock config registers:

              These registers contain enable, reset & divider tables for the, cpu,
@@ -32,6 +33,12 @@ properties: 
              mss pll dri registers:

              Block of registers responsible for dynamic reconfiguration of the mss

              pll

        deprecated: true

      - items:

          - description: |

              mss pll dri registers:

              Block of registers responsible for dynamic reconfiguration of the mss

              pll



  clocks:

    maxItems: 1
@@ -69,11 +76,12 @@ examples: 
  - |

    #include <dt-bindings/clock/microchip,mpfs-clock.h>

    soc {

            #address-cells = <2>;

            #size-cells = <2>;

            clkcfg: clock-controller@20002000 {

            #address-cells = <1>;

            #size-cells = <1>;



            clkcfg: clock-controller@3E001000 {

                compatible = "microchip,mpfs-clkcfg";

                reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;

                reg = <0x3E001000 0x1000>;

                clocks = <&ref>;

                #clock-cells = <1>;

        };

drivers/clk/clk-lan966x.c

+0 −2
Original line number Diff line number Diff line
@@ -16,8 +16,6 @@ 
#include <linux/platform_device.h>

#include <linux/slab.h>



#include <dt-bindings/clock/microchip,lan966x.h>



#define GCK_ENA         BIT(0)

#define GCK_SRC_SEL     GENMASK(9, 8)

#define GCK_PRESCALER   GENMASK(23, 16)

drivers/clk/microchip/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -7,6 +7,8 @@ config MCHP_CLK_MPFS 
	bool "Clk driver for PolarFire SoC"

	depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST

	default ARCH_MICROCHIP_POLARFIRE

	depends on MFD_SYSCON

	select AUXILIARY_BUS

	select REGMAP_MMIO

	help

	  Supports Clock Configuration for PolarFire SoC

drivers/clk/microchip/clk-mpfs.c

+184 −43
Original line number Diff line number Diff line
@@ -4,10 +4,13 @@ 
 *

 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.

 */

#include <linux/cleanup.h>

#include <linux/clk-provider.h>

#include <linux/io.h>

#include <linux/mfd/syscon.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/regmap.h>

#include <dt-bindings/clock/microchip,mpfs-clock.h>

#include <soc/microchip/mpfs.h>
@@ -30,6 +33,14 @@ 
#define MSSPLL_POSTDIV_WIDTH	0x07u

#define MSSPLL_FIXED_DIV	4u



static const struct regmap_config mpfs_clk_regmap_config = {

	.reg_bits = 32,

	.reg_stride = 4,

	.val_bits = 32,

	.val_format_endian = REGMAP_ENDIAN_LITTLE,

	.max_register = REG_SUBBLK_RESET_CR,

};



/*

 * This clock ID is defined here, rather than the binding headers, as it is an

 * internal clock only, and therefore has no consumers in other peripheral
@@ -39,6 +50,7 @@ 


struct mpfs_clock_data {

	struct device *dev;

	struct regmap *regmap;

	void __iomem *base;

	void __iomem *msspll_base;

	struct clk_hw_onecell_data hw_data;
@@ -67,21 +79,39 @@ struct mpfs_msspll_out_hw_clock { 


#define to_mpfs_msspll_out_clk(_hw) container_of(_hw, struct mpfs_msspll_out_hw_clock, hw)



struct mpfs_cfg_clock {

	struct regmap *map;

	const struct clk_div_table *table;

	u8 map_offset;

	u8 shift;

	u8 width;

	u8 flags;

};



struct mpfs_cfg_hw_clock {

	struct clk_divider cfg;

	struct clk_init_data init;

	struct clk_hw hw;

	struct mpfs_cfg_clock cfg;

	unsigned int id;

	u32 reg_offset;

};



#define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw)



struct mpfs_periph_clock {

	struct regmap *map;

	u8 map_offset;

	u8 shift;

};



struct mpfs_periph_hw_clock {

	struct clk_gate periph;

	struct clk_hw hw;

	struct mpfs_periph_clock periph;

	unsigned int id;

};



#define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw)



/*

 * mpfs_clk_lock prevents anything else from writing to the

 * mpfs clk block while a software locked register is being written.

 * Protects MSSPLL outputs, since there's two to a register

 */

static DEFINE_SPINLOCK(mpfs_clk_lock);
@@ -219,16 +249,61 @@ static int mpfs_clk_register_msspll_outs(struct device *dev, 
/*

 * "CFG" clocks

 */

static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate)

{

	struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);

	struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;

	u32 val;



	regmap_read(cfg->map, cfg->map_offset, &val);

	val >>= cfg->shift;

	val &= clk_div_mask(cfg->width);



	return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width);

}



static int mpfs_cfg_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)

{

	struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);

	struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;



	return divider_determine_rate(hw, req, cfg->table, cfg->width, 0);

}



static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)

{

	struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);

	struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;

	int divider_setting;

	u32 val;

	u32 mask;



	divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0);



	if (divider_setting < 0)

		return divider_setting;



	mask = clk_div_mask(cfg->width) << cfg->shift;

	val = divider_setting << cfg->shift;

	regmap_update_bits(cfg->map, cfg->map_offset, val, mask);



	return 0;

}



static const struct clk_ops mpfs_clk_cfg_ops = {

	.recalc_rate = mpfs_cfg_clk_recalc_rate,

	.determine_rate = mpfs_cfg_clk_determine_rate,

	.set_rate = mpfs_cfg_clk_set_rate,

};



#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) {	\

	.id = _id,								\

	.cfg.shift = _shift,							\

	.cfg.width = _width,							\

	.cfg.table = _table,							\

	.reg_offset = _offset,								\

	.cfg.map_offset = _offset,						\

	.cfg.flags = _flags,							\

	.cfg.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0),		\

	.cfg.lock = &mpfs_clk_lock,							\

	.hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0),		\

}



#define CLK_CPU_OFFSET		0u
@@ -248,10 +323,10 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { 
		.cfg.shift = 0,

		.cfg.width = 12,

		.cfg.table = mpfs_div_rtcref_table,

		.reg_offset = REG_RTC_CLOCK_CR,

		.cfg.map_offset = REG_RTC_CLOCK_CR,

		.cfg.flags = CLK_DIVIDER_ONE_BASED,

		.cfg.hw.init =

			CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, 0),

		.hw.init =

			CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0),

	}

};
@@ -264,14 +339,14 @@ static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock * 
	for (i = 0; i < num_clks; i++) {

		struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i];



		cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset;

		ret = devm_clk_hw_register(dev, &cfg_hw->cfg.hw);

		cfg_hw->cfg.map = data->regmap;

		ret = devm_clk_hw_register(dev, &cfg_hw->hw);

		if (ret)

			return dev_err_probe(dev, ret, "failed to register clock id: %d\n",

					     cfg_hw->id);



		id = cfg_hw->id;

		data->hw_data.hws[id] = &cfg_hw->cfg.hw;

		data->hw_data.hws[id] = &cfg_hw->hw;

	}



	return 0;
@@ -281,15 +356,50 @@ static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock * 
 * peripheral clocks - devices connected to axi or ahb buses.

 */



static int mpfs_periph_clk_enable(struct clk_hw *hw)

{

	struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);

	struct mpfs_periph_clock *periph = &periph_hw->periph;



	regmap_update_bits(periph->map, periph->map_offset,

			   BIT(periph->shift), BIT(periph->shift));



	return 0;

}



static void mpfs_periph_clk_disable(struct clk_hw *hw)

{

	struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);

	struct mpfs_periph_clock *periph = &periph_hw->periph;



	regmap_update_bits(periph->map, periph->map_offset, BIT(periph->shift), 0);

}



static int mpfs_periph_clk_is_enabled(struct clk_hw *hw)

{

	struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);

	struct mpfs_periph_clock *periph = &periph_hw->periph;

	u32 val;



	regmap_read(periph->map, periph->map_offset, &val);



	return !!(val & BIT(periph->shift));

}



static const struct clk_ops mpfs_periph_clk_ops = {

	.enable = mpfs_periph_clk_enable,

	.disable = mpfs_periph_clk_disable,

	.is_enabled = mpfs_periph_clk_is_enabled,

};



#define CLK_PERIPH(_id, _name, _parent, _shift, _flags) {				\

	.id = _id,									\

	.periph.bit_idx = _shift,						\

	.periph.hw.init = CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops,		\

				  _flags),					\

	.periph.lock = &mpfs_clk_lock,						\

	.periph.map_offset = REG_SUBBLK_CLOCK_CR,					\

	.periph.shift = _shift,								\

	.hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, _flags),	\

}



#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw)

#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].hw)



/*

 * Critical clocks:
@@ -346,19 +456,55 @@ static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_c 
	for (i = 0; i < num_clks; i++) {

		struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i];



		periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR;

		ret = devm_clk_hw_register(dev, &periph_hw->periph.hw);

		periph_hw->periph.map = data->regmap;

		ret = devm_clk_hw_register(dev, &periph_hw->hw);

		if (ret)

			return dev_err_probe(dev, ret, "failed to register clock id: %d\n",

					     periph_hw->id);



		id = periph_hws[i].id;

		data->hw_data.hws[id] = &periph_hw->periph.hw;

		data->hw_data.hws[id] = &periph_hw->hw;

	}



	return 0;

}



static inline int mpfs_clk_syscon_probe(struct mpfs_clock_data *clk_data,

					struct platform_device *pdev)

{

	clk_data->regmap = syscon_regmap_lookup_by_compatible("microchip,mpfs-mss-top-sysreg");

	if (IS_ERR(clk_data->regmap))

		return PTR_ERR(clk_data->regmap);



	clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 0);

	if (IS_ERR(clk_data->msspll_base))

		return PTR_ERR(clk_data->msspll_base);



	return 0;

}



static inline int mpfs_clk_old_format_probe(struct mpfs_clock_data *clk_data,

					    struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;



	dev_warn(&pdev->dev, "falling back to old devicetree format");



	clk_data->base = devm_platform_ioremap_resource(pdev, 0);

	if (IS_ERR(clk_data->base))

		return PTR_ERR(clk_data->base);



	clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1);

	if (IS_ERR(clk_data->msspll_base))

		return PTR_ERR(clk_data->msspll_base);



	clk_data->regmap = devm_regmap_init_mmio(dev, clk_data->base, &mpfs_clk_regmap_config);

	if (IS_ERR(clk_data->regmap))

		return PTR_ERR(clk_data->regmap);



	return mpfs_reset_controller_register(dev, clk_data->regmap);

}



static int mpfs_clk_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;
@@ -374,13 +520,12 @@ static int mpfs_clk_probe(struct platform_device *pdev) 
	if (!clk_data)

		return -ENOMEM;



	clk_data->base = devm_platform_ioremap_resource(pdev, 0);

	if (IS_ERR(clk_data->base))

		return PTR_ERR(clk_data->base);



	clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1);

	if (IS_ERR(clk_data->msspll_base))

		return PTR_ERR(clk_data->msspll_base);

	ret = mpfs_clk_syscon_probe(clk_data, pdev);

	if (ret) {

		ret = mpfs_clk_old_format_probe(clk_data, pdev);

		if (ret)

			return ret;

	}



	clk_data->hw_data.num = num_clks;

	clk_data->dev = dev;
@@ -406,11 +551,7 @@ static int mpfs_clk_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data);

	if (ret)

		return ret;



	return mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_RESET_CR);

	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data);

}



static const struct of_device_id mpfs_clk_of_match_table[] = {

drivers/reset/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -200,6 +200,7 @@ config RESET_PISTACHIO 
config RESET_POLARFIRE_SOC

	bool "Microchip PolarFire SoC (MPFS) Reset Driver"

	depends on MCHP_CLK_MPFS

	depends on MFD_SYSCON

	select AUXILIARY_BUS

	default MCHP_CLK_MPFS

	help