Commit b5bad8c1 authored by Dave Airlie's avatar Dave Airlie
Browse files

nouveau/gsp: move to 535.113.01 



This moves the initial effort to the latest 535 firmware.

The gsp msg structs have changed, and the message passing also.
The wpr also seems to have some struct changes.

This version of the firmware will be what we are stuck on for a while,
until we can refactor the driver and work out a better path forward.

Reviewed-by: default avatarDanilo Krummrich <dakr@redhat.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 7e6bd640

drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/alloc/alloc_channel.h→drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/sdk/nvidia/inc/alloc/alloc_channel.h

+11 −2
Original line number Diff line number Diff line 
#ifndef __src_common_sdk_nvidia_inc_alloc_alloc_channel_h__

#define __src_common_sdk_nvidia_inc_alloc_alloc_channel_h__

#include <nvrm/535.54.03/common/sdk/nvidia/inc/nvlimits.h>

#include <nvrm/535.113.01/common/sdk/nvidia/inc/nvlimits.h>



/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */

/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */



/*

 * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
@@ -116,6 +116,9 @@ typedef struct NV_MEMORY_DESC_PARAMS { 
#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_FALSE                    0x00000000

#define NVOS04_FLAGS_SKIP_CTXBUFFER_ALLOC_TRUE                     0x00000001



#define CC_CHAN_ALLOC_IV_SIZE_DWORD    3U

#define CC_CHAN_ALLOC_NONCE_SIZE_DWORD 8U



typedef struct NV_CHANNEL_ALLOC_PARAMS {



    NvHandle hObjectError; // error context DMA
@@ -154,6 +157,12 @@ typedef struct NV_CHANNEL_ALLOC_PARAMS { 
    NV_DECLARE_ALIGNED(NV_MEMORY_DESC_PARAMS eccErrorNotifierMem, 8); // reserved

    NvU32    ProcessID;                 // reserved

    NvU32    SubProcessID;                 // reserved

    // IV used for CPU-side encryption / GPU-side decryption.

    NvU32    encryptIv[CC_CHAN_ALLOC_IV_SIZE_DWORD];          // reserved

    // IV used for CPU-side decryption / GPU-side encryption.

    NvU32    decryptIv[CC_CHAN_ALLOC_IV_SIZE_DWORD];          // reserved

    // Nonce used CPU-side signing / GPU-side signature verification.

    NvU32    hmacNonce[CC_CHAN_ALLOC_NONCE_SIZE_DWORD];       // reserved

} NV_CHANNEL_ALLOC_PARAMS;



typedef NV_CHANNEL_ALLOC_PARAMS NV_CHANNELGPFIFO_ALLOCATION_PARAMETERS;

drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/class/cl0000.h→drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/sdk/nvidia/inc/class/cl0000.h

+2 −2
Original line number Diff line number Diff line 
#ifndef __src_common_sdk_nvidia_inc_class_cl0000_h__

#define __src_common_sdk_nvidia_inc_class_cl0000_h__

#include <nvrm/535.54.03/common/sdk/nvidia/inc/nvlimits.h>

#include <nvrm/535.113.01/common/sdk/nvidia/inc/nvlimits.h>



/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */

/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */



/*

 * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/class/cl0005.h→drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/sdk/nvidia/inc/class/cl0005.h

+1 −1
Original line number Diff line number Diff line 
#ifndef __src_common_sdk_nvidia_inc_class_cl0005_h__

#define __src_common_sdk_nvidia_inc_class_cl0005_h__



/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */

/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */



/*

 * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/class/cl0080.h→drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/sdk/nvidia/inc/class/cl0080.h

+1 −1
Original line number Diff line number Diff line 
#ifndef __src_common_sdk_nvidia_inc_class_cl0080_h__

#define __src_common_sdk_nvidia_inc_class_cl0080_h__



/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */

/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */



/*

 * SPDX-FileCopyrightText: Copyright (c) 2001-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/class/cl2080.h→drivers/gpu/drm/nouveau/include/nvrm/535.113.01/common/sdk/nvidia/inc/class/cl2080.h

+1 −1
Original line number Diff line number Diff line 
#ifndef __src_common_sdk_nvidia_inc_class_cl2080_h__

#define __src_common_sdk_nvidia_inc_class_cl2080_h__



/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */

/* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */



/*

 * SPDX-FileCopyrightText: Copyright (c) 2002-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.