Commit b6030177 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2025-04-11' of... 

Merge tag 'drm-intel-next-2025-04-11' of https://gitlab.freedesktop.org/drm/i915/kernel

 into drm-next

Cross-subsystem Changes:
- Update GVT MAINTAINERS (Jani)

Driver Changes:
- Updates for xe3lpd display (Gustavo)
- Fix link training interrupted by HPD pulse (Imre)
- Watermark bound checks for DSC (Ankit)
- VRR Refactor and other fixes and improvements (Ankit)
- More conversions towards intel_display struct (Gustavo, Jani)
- Other clean-up patches towards a display separation (Jani)
- Maintain asciibetical order for HAS_* macros (Ankit)
- Fixes around probe/initialization (Janusz)
- Fix build and doc build issue (Yue, Rodrigo)
- DSI related fixes (Suraj, William, Jani)
- Improve DC6 entry counter (Mohammed)
- Fix xe2hpd memory type identification (Vivek)
- PSR related fixes and improvements (Animesh, Jouni)
- DP MST related fixes and improvements (Imre)
- Fix scanline_offset for LNL+/BMG+ (Ville)
- Some gvt related fixes and changes (Ville, Jani)
- Some PLL code adjustment (Ville)
- Display wa addition (Vinod)
- DRAM type logging (Lucas)
- Pimp the initial FB readout (Ville)
- Some sagv/bw cleanup (Ville)
- Remove i915_display_capabilities debugfs entry (Jani)
- Move PCH type to display caps debugfs entry (Jani)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://lore.kernel.org/r/Z_kTqPX5Mjruq1pL@intel.com
parents 683058df 1954629d

MAINTAINERS

+3 −6
Original line number Diff line number Diff line
@@ -11920,13 +11920,10 @@ F: drivers/gpio/gpio-tangier.c 
F:	drivers/gpio/gpio-tangier.h









INTEL GVT-g DRIVERS (Intel GPU Virtualization)









M:	Zhenyu Wang <zhenyuw.linux@gmail.com>









M:	Zhi Wang <zhi.wang.linux@gmail.com>









L:	intel-gvt-dev@lists.freedesktop.org









L:	intel-gfx@lists.freedesktop.org









S:	Supported









R:	Zhenyu Wang <zhenyuw.linux@gmail.com>









R:	Zhi Wang <zhi.wang.linux@gmail.com>









S:	Odd Fixes









W:	https://github.com/intel/gvt-linux/wiki









T:	git https://github.com/intel/gvt-linux.git









F:	drivers/gpu/drm/i915/gvt/

















INTEL HID EVENT DRIVER
































drivers/char/agp/intel-gtt.c



+55
−0






























Original line number
Diff line number
Diff line







@@ -53,6 +53,7 @@ struct intel_gtt_driver {







	 * of the mmio register file, that's done in the generic code. */









	void (*cleanup)(void);









	void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);









	dma_addr_t (*read_entry)(unsigned int entry, bool *is_present, bool *is_local);









	/* Flags is a more or less chipset specific opaque value.









	 * For chipsets that need to support old ums (non-gem) code, this









	 * needs to be identical to the various supported agp memory types! */








@@ -336,6 +337,19 @@ static void i810_write_entry(dma_addr_t addr, unsigned int entry,







	writel_relaxed(addr | pte_flags, intel_private.gtt + entry);









}



















static dma_addr_t i810_read_entry(unsigned int entry,









				  bool *is_present, bool *is_local)









{









	u32 val;



















	val = readl(intel_private.gtt + entry);



















	*is_present = val & I810_PTE_VALID;









	*is_local = val & I810_PTE_LOCAL;



















	return val & ~0xfff;









}



















static resource_size_t intel_gtt_stolen_size(void)









{









	u16 gmch_ctrl;








@@ -741,6 +755,19 @@ static void i830_write_entry(dma_addr_t addr, unsigned int entry,







	writel_relaxed(addr | pte_flags, intel_private.gtt + entry);









}



















static dma_addr_t i830_read_entry(unsigned int entry,









				  bool *is_present, bool *is_local)









{









	u32 val;



















	val = readl(intel_private.gtt + entry);



















	*is_present = val & I810_PTE_VALID;









	*is_local = false;



















	return val & ~0xfff;









}



















bool intel_gmch_enable_gtt(void)









{









	u8 __iomem *reg;








@@ -878,6 +905,13 @@ void intel_gmch_gtt_insert_sg_entries(struct sg_table *st,







}









EXPORT_SYMBOL(intel_gmch_gtt_insert_sg_entries);



















dma_addr_t intel_gmch_gtt_read_entry(unsigned int pg,









				     bool *is_present, bool *is_local)









{









	return intel_private.driver->read_entry(pg, is_present, is_local);









}









EXPORT_SYMBOL(intel_gmch_gtt_read_entry);



















#if IS_ENABLED(CONFIG_AGP_INTEL)









static void intel_gmch_gtt_insert_pages(unsigned int first_entry,









					unsigned int num_entries,








@@ -1126,6 +1160,19 @@ static void i965_write_entry(dma_addr_t addr,







	writel_relaxed(addr | pte_flags, intel_private.gtt + entry);









}



















static dma_addr_t i965_read_entry(unsigned int entry,









				  bool *is_present, bool *is_local)









{









	u64 val;



















	val = readl(intel_private.gtt + entry);



















	*is_present = val & I810_PTE_VALID;









	*is_local = false;



















	return ((val & 0xf0) << 28) | (val & ~0xfff);









}



















static int i9xx_setup(void)









{









	phys_addr_t reg_addr;








@@ -1187,6 +1234,7 @@ static const struct intel_gtt_driver i81x_gtt_driver = {







	.cleanup = i810_cleanup,









	.check_flags = i830_check_flags,









	.write_entry = i810_write_entry,









	.read_entry = i810_read_entry,









};









static const struct intel_gtt_driver i8xx_gtt_driver = {









	.gen = 2,








@@ -1194,6 +1242,7 @@ static const struct intel_gtt_driver i8xx_gtt_driver = {







	.setup = i830_setup,









	.cleanup = i830_cleanup,









	.write_entry = i830_write_entry,









	.read_entry = i830_read_entry,









	.dma_mask_size = 32,









	.check_flags = i830_check_flags,









	.chipset_flush = i830_chipset_flush,








@@ -1205,6 +1254,7 @@ static const struct intel_gtt_driver i915_gtt_driver = {







	.cleanup = i9xx_cleanup,









	/* i945 is the last gpu to need phys mem (for overlay and cursors). */









	.write_entry = i830_write_entry,









	.read_entry = i830_read_entry,









	.dma_mask_size = 32,









	.check_flags = i830_check_flags,









	.chipset_flush = i9xx_chipset_flush,








@@ -1215,6 +1265,7 @@ static const struct intel_gtt_driver g33_gtt_driver = {







	.setup = i9xx_setup,









	.cleanup = i9xx_cleanup,









	.write_entry = i965_write_entry,









	.read_entry = i965_read_entry,









	.dma_mask_size = 36,









	.check_flags = i830_check_flags,









	.chipset_flush = i9xx_chipset_flush,








@@ -1225,6 +1276,7 @@ static const struct intel_gtt_driver pineview_gtt_driver = {







	.setup = i9xx_setup,









	.cleanup = i9xx_cleanup,









	.write_entry = i965_write_entry,









	.read_entry = i965_read_entry,









	.dma_mask_size = 36,









	.check_flags = i830_check_flags,









	.chipset_flush = i9xx_chipset_flush,








@@ -1235,6 +1287,7 @@ static const struct intel_gtt_driver i965_gtt_driver = {







	.setup = i9xx_setup,









	.cleanup = i9xx_cleanup,









	.write_entry = i965_write_entry,









	.read_entry = i965_read_entry,









	.dma_mask_size = 36,









	.check_flags = i830_check_flags,









	.chipset_flush = i9xx_chipset_flush,








@@ -1244,6 +1297,7 @@ static const struct intel_gtt_driver g4x_gtt_driver = {







	.setup = i9xx_setup,









	.cleanup = i9xx_cleanup,









	.write_entry = i965_write_entry,









	.read_entry = i965_read_entry,









	.dma_mask_size = 36,









	.check_flags = i830_check_flags,









	.chipset_flush = i9xx_chipset_flush,








@@ -1254,6 +1308,7 @@ static const struct intel_gtt_driver ironlake_gtt_driver = {







	.setup = i9xx_setup,









	.cleanup = i9xx_cleanup,









	.write_entry = i965_write_entry,









	.read_entry = i965_read_entry,









	.dma_mask_size = 36,









	.check_flags = i830_check_flags,









	.chipset_flush = i9xx_chipset_flush,
































drivers/gpu/drm/i915/Makefile



+1
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@@ -247,6 +247,7 @@ i915-y += \







	display/intel_display_power_map.o \









	display/intel_display_power_well.o \









	display/intel_display_reset.o \









	display/intel_display_rpm.o \









	display/intel_display_rps.o \









	display/intel_display_snapshot.o \









	display/intel_display_wa.o \
































drivers/gpu/drm/i915/display/dvo_ch7017.c



+2
−0






























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@@ -25,6 +25,8 @@







 *









 */



















#include <drm/drm_print.h>



















#include "intel_display_types.h"









#include "intel_dvo_dev.h"










































drivers/gpu/drm/i915/display/dvo_ch7xxx.c



+2
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@@ -26,6 +26,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

















**************************************************************************/



















#include <drm/drm_print.h>



















#include "intel_display_types.h"









#include "intel_dvo_dev.h"