Unverified Commit b609a15e authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Krzysztof Wilczyński
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PCI: mediatek-gen3: Add support for restricting link width 

Add support for restricting the port's link width by specifying
the num-lanes devicetree property in the PCIe node.

The setting is done in the GEN_SETTINGS register (in the driver
named as PCIE_SETTING_REG), where each set bit in [11:8] activates
a set of lanes (from bits 11 to 8 respectively, x16/x8/x4/x2).

Link: https://lore.kernel.org/r/20241104114935.172908-3-angelogioacchino.delregno@collabora.com


Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: default avatarKrzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: default avatarFei Shao <fshao@chromium.org>
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
parent ade7da14

drivers/pci/controller/pcie-mediatek-gen3.c

+20 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ 
#define PCIE_BASE_CFG_SPEED		GENMASK(15, 8)



#define PCIE_SETTING_REG		0x80

#define PCIE_SETTING_LINK_WIDTH		GENMASK(11, 8)

#define PCIE_SETTING_GEN_SUPPORT	GENMASK(14, 12)

#define PCIE_PCI_IDS_1			0x9c

#define PCI_CLASS(class)		(class << 8)
@@ -168,6 +169,7 @@ struct mtk_msi_set { 
 * @clks: PCIe clocks

 * @num_clks: PCIe clocks count for this port

 * @max_link_speed: Maximum link speed (PCIe Gen) for this port

 * @num_lanes: Number of PCIe lanes for this port

 * @irq: PCIe controller interrupt number

 * @saved_irq_state: IRQ enable state saved at suspend time

 * @irq_lock: lock protecting IRQ register access
@@ -189,6 +191,7 @@ struct mtk_gen3_pcie { 
	struct clk_bulk_data *clks;

	int num_clks;

	u8 max_link_speed;

	u8 num_lanes;



	int irq;

	u32 saved_irq_state;
@@ -401,6 +404,14 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie) 
			val |= FIELD_PREP(PCIE_SETTING_GEN_SUPPORT,

					  GENMASK(pcie->max_link_speed - 2, 0));

	}

	if (pcie->num_lanes) {

		val &= ~PCIE_SETTING_LINK_WIDTH;



		/* Zero means one lane, each bit activates x2/x4/x8/x16 */

		if (pcie->num_lanes > 1)

			val |= FIELD_PREP(PCIE_SETTING_LINK_WIDTH,

					  GENMASK(fls(pcie->num_lanes >> 2), 0));

	};

	writel_relaxed(val, pcie->base + PCIE_SETTING_REG);



	/* Set Link Control 2 (LNKCTL2) speed restriction, if any */
@@ -838,6 +849,7 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) 
	struct device *dev = pcie->dev;

	struct platform_device *pdev = to_platform_device(dev);

	struct resource *regs;

	u32 num_lanes;



	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");

	if (!regs)
@@ -883,6 +895,14 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie) 
		return pcie->num_clks;

	}



       ret = of_property_read_u32(dev->of_node, "num-lanes", &num_lanes);

       if (ret == 0) {

	       if (num_lanes == 0 || num_lanes > 16 || (num_lanes != 1 && num_lanes % 2))

			dev_warn(dev, "invalid num-lanes, using controller defaults\n");

	       else

			pcie->num_lanes = num_lanes;

       }



	return 0;

}