Commit b6ce504c authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Rob Clark
Browse files

drm/msm/a6xx: Resolve the meaning of rgb565_predicator 



It's supposed to be on when the UBWC encoder version is >= 4.0.
Drop the per-GPU assignments.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/660975/


Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
parent c59e9c96

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+2 −5
Original line number Diff line number Diff line
@@ -611,7 +611,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) 
	if (IS_ERR(gpu->common_ubwc_cfg))

		return PTR_ERR(gpu->common_ubwc_cfg);



	gpu->ubwc_config.rgb565_predicator = 0;

	gpu->ubwc_config.min_acc_len = 0;

	gpu->ubwc_config.ubwc_swizzle = 0x6;

	gpu->ubwc_config.macrotile_mode = 0;
@@ -638,7 +637,6 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) 


	if (adreno_is_a623(gpu)) {

		gpu->ubwc_config.highest_bank_bit = 16;

		gpu->ubwc_config.rgb565_predicator = 1;

		gpu->ubwc_config.macrotile_mode = 1;

	}
@@ -652,13 +650,11 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu) 
	    adreno_is_a740_family(gpu)) {

		/* TODO: get ddr type from bootloader and use 2 for LPDDR4 */

		gpu->ubwc_config.highest_bank_bit = 16;

		gpu->ubwc_config.rgb565_predicator = 1;

		gpu->ubwc_config.macrotile_mode = 1;

	}



	if (adreno_is_a663(gpu)) {

		gpu->ubwc_config.highest_bank_bit = 13;

		gpu->ubwc_config.rgb565_predicator = 1;

		gpu->ubwc_config.macrotile_mode = 1;

		gpu->ubwc_config.ubwc_swizzle = 0x4;

	}
@@ -687,6 +683,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 
	 */

	BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13);

	u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13;

	bool rgb565_predicator = cfg->ubwc_enc_version >= UBWC_4_0;

	u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & BIT(1));

	bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg);

	bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
@@ -699,7 +696,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 


	gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,

		  level2_swizzling_dis << 12 |

		  adreno_gpu->ubwc_config.rgb565_predicator << 11 |

		  rgb565_predicator << 11 |

		  hbb_hi << 10 | amsbc << 4 |

		  adreno_gpu->ubwc_config.min_acc_len << 3 |

		  hbb_lo << 1 | ubwc_mode);