Commit b6d1a063 authored by Sonny Jiang's avatar Sonny Jiang Committed by Alex Deucher
Browse files

drm/amdgpu: add VCN_5_0_0 IP block support 



Add VCN_5_0_0 IP init, ring functions, DPG support.

v2: squash in warning fixes (Alex)
v3: squash in block and ring init, boot, doorbell enablement,
    DPG support (Alex)

Signed-off-by: default avatarSonny Jiang <sonny.jiang@amd.com>
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 816dae1d

drivers/gpu/drm/amd/amdgpu/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -209,6 +209,7 @@ amdgpu-y += \ 
	vcn_v4_0.o \

	vcn_v4_0_3.o \

	vcn_v4_0_5.o \

	vcn_v5_0_0.o \

	amdgpu_jpeg.o \

	jpeg_v1_0.o \

	jpeg_v2_0.o \

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

+42 −0
Original line number Diff line number Diff line
@@ -160,6 +160,48 @@ 
		}                                                                     \

	} while (0)



#define SOC24_DPG_MODE_OFFSET(ip, inst_idx, reg)						\

	({											\

		uint32_t internal_reg_offset, addr;						\

		bool video_range, aon_range;				\

												\

		addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg);		\

		addr <<= 2;									\

		video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS)) &&			\

				((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS + 0x2600)))));	\

		aon_range   = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS)) &&			\

				((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS + 0x600)))));		\

		if (video_range)								\

			internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS) +	\

				(VCN_VID_IP_ADDRESS));						\

		else if (aon_range)								\

			internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS) +	\

				(VCN_AON_IP_ADDRESS));						\

		else										\

			internal_reg_offset = (0xFFFFF & addr);					\

												\

		internal_reg_offset >>= 2;							\

	})



#define WREG32_SOC24_DPG_MODE(inst_idx, offset, value, mask_en, indirect)		\

	do {										\

		if (!indirect) {							\

			WREG32_SOC15(VCN, GET_INST(VCN, inst_idx),			\

				     regUVD_DPG_LMA_DATA, value);			\

			WREG32_SOC15(							\

				VCN, GET_INST(VCN, inst_idx),				\

				regUVD_DPG_LMA_CTL,					\

				(0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT |		\

				 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT |		\

				 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT));	\

		} else {								\

			*adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ =		\

				offset;							\

			*adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ =		\

				value;							\

		}									\

	} while (0)



#define AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE (1 << 2)

#define AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT (1 << 4)

#define AMDGPU_VCN_FW_SHARED_FLAG_0_RB	(1 << 6)

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

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+1339 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.h

0 → 100644
+37 −0
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/*

 * Copyright 2023 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef __VCN_V5_0_0_H__

#define __VCN_V5_0_0_H__



#define VCN_VID_SOC_ADDRESS                        0x1FC00

#define VCN_AON_SOC_ADDRESS                        0x1F800

#define VCN1_VID_SOC_ADDRESS                       0x48300

#define VCN1_AON_SOC_ADDRESS                       0x48000



#define VCN_VID_IP_ADDRESS                         0x0

#define VCN_AON_IP_ADDRESS                         0x30000



extern const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block;



#endif /* __VCN_V5_0_0_H__ */