Commit b6f61a31 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'net-tn40xx-add-support-for-aqr105-based-cards' 

Hans-Frieder Vogt says:

====================
net: tn40xx: add support for AQR105 based cards

This patch series adds support to the Tehuti tn40xx driver for TN9510 cards
which combine a TN4010 MAC with an Aquantia AQR105.
It is an update of the patch series "net: tn40xx: add support for AQR105
based cards", addressing review comments and generally cleaning up the series.

The patch was tested on a Tehuti TN9510 card (1fc9:4025:1fc9:3015).

v6: https://lore.kernel.org/20250318-tn9510-v3a-v6-0-808a9089d24b@gmx.net
v5: https://lore.kernel.org/20250222-tn9510-v3a-v5-0-99365047e309@gmx.net
v4: https://lore.kernel.org/20241221-tn9510-v3a-v4-0-dafff89ba7a7@gmx.net
v3: https://lore.kernel.org/20241217-tn9510-v3a-v3-0-4d5ef6f686e0@gmx.net
v2: https://lore.kernel.org/trinity-602c050f-bc76-4557-9824-252b0de48659-1726429697171@3c-app-gmx-bap07
v1: https://lore.kernel.org/trinity-33332a4a-1c44-46b7-8526-b53b1a94ffc2-1726082106356@3c-app-gmx-bs04
====================

Link: https://patch.msgid.link/20250322-tn9510-v3a-v7-0-672a9a3d8628@gmx.net


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents e2ac75a8 53377b5c

drivers/net/ethernet/tehuti/tn40.c

+8 −1
Original line number Diff line number Diff line
@@ -1778,7 +1778,7 @@ static int tn40_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 
	ret = tn40_phy_register(priv);

	if (ret) {

		dev_err(&pdev->dev, "failed to set up PHY.\n");

		goto err_free_irq;

		goto err_cleanup_swnodes;

	}



	ret = tn40_priv_init(priv);
@@ -1795,6 +1795,8 @@ static int tn40_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 
	return 0;

err_unregister_phydev:

	tn40_phy_unregister(priv);

err_cleanup_swnodes:

	tn40_swnodes_cleanup(priv);

err_free_irq:

	pci_free_irq_vectors(pdev);

err_unset_drvdata:
@@ -1816,6 +1818,7 @@ static void tn40_remove(struct pci_dev *pdev) 
	unregister_netdev(ndev);



	tn40_phy_unregister(priv);

	tn40_swnodes_cleanup(priv);

	pci_free_irq_vectors(priv->pdev);

	pci_set_drvdata(pdev, NULL);

	iounmap(priv->regs);
@@ -1832,6 +1835,10 @@ static const struct pci_device_id tn40_id_table[] = { 
			 PCI_VENDOR_ID_ASUSTEK, 0x8709) },

	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_TEHUTI, 0x4022,

			 PCI_VENDOR_ID_EDIMAX, 0x8103) },

	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_TEHUTI, PCI_DEVICE_ID_TEHUTI_TN9510,

			 PCI_VENDOR_ID_TEHUTI, 0x3015) },

	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_TEHUTI, PCI_DEVICE_ID_TEHUTI_TN9510,

			 PCI_VENDOR_ID_EDIMAX, 0x8102) },

	{ }

};

drivers/net/ethernet/tehuti/tn40.h

+33 −0
Original line number Diff line number Diff line
@@ -4,10 +4,13 @@ 
#ifndef _TN40_H_

#define _TN40_H_



#include <linux/property.h>

#include "tn40_regs.h"



#define TN40_DRV_NAME "tn40xx"



#define PCI_DEVICE_ID_TEHUTI_TN9510	0x4025



#define TN40_MDIO_SPEED_1MHZ (1)

#define TN40_MDIO_SPEED_6MHZ (6)
@@ -102,10 +105,39 @@ struct tn40_txdb { 
	int size; /* Number of elements in the db */

};



#define NODE_PROP(_NAME, _PROP)	(		\

	(const struct software_node) {		\

		.name = _NAME,			\

		.properties = _PROP,		\

	})



#define NODE_PAR_PROP(_NAME, _PAR, _PROP)	(	\

	(const struct software_node) {		\

		.name = _NAME,			\

		.parent = _PAR,			\

		.properties = _PROP,		\

	})



enum tn40_swnodes {

	SWNODE_MDIO,

	SWNODE_PHY,

	SWNODE_MAX

};



struct tn40_nodes {

	char phy_name[32];

	char mdio_name[32];

	struct property_entry phy_props[3];

	struct software_node swnodes[SWNODE_MAX];

	const struct software_node *group[SWNODE_MAX + 1];

};



struct tn40_priv {

	struct net_device *ndev;

	struct pci_dev *pdev;



	struct tn40_nodes nodes;



	struct napi_struct napi;

	/* RX FIFOs: 1 for data (full) descs, and 2 for free descs */

	struct tn40_rxd_fifo rxd_fifo0;
@@ -225,6 +257,7 @@ static inline void tn40_write_reg(struct tn40_priv *priv, u32 reg, u32 val) 


int tn40_set_link_speed(struct tn40_priv *priv, u32 speed);



void tn40_swnodes_cleanup(struct tn40_priv *priv);

int tn40_mdiobus_init(struct tn40_priv *priv);



int tn40_phy_register(struct tn40_priv *priv);

drivers/net/ethernet/tehuti/tn40_mdio.c

+81 −3
Original line number Diff line number Diff line
@@ -14,6 +14,8 @@ 
	 (FIELD_PREP(TN40_MDIO_PRTAD_MASK, (port))))

#define TN40_MDIO_CMD_READ BIT(15)



#define AQR105_FIRMWARE "tehuti/aqr105-tn40xx.cld"



static void tn40_mdio_set_speed(struct tn40_priv *priv, u32 speed)

{

	void __iomem *regs = priv->regs;
@@ -111,6 +113,56 @@ static int tn40_mdio_write_c45(struct mii_bus *mii_bus, int addr, int devnum, 
	return  tn40_mdio_write(mii_bus->priv, addr, devnum, regnum, val);

}



/* registers an mdio node and an aqr105 PHY at address 1

 * tn40_mdio-%id {

 *	ethernet-phy@1 {

 *		compatible = "ethernet-phy-id03a1.b4a3";

 *		reg = <1>;

 *		firmware-name = AQR105_FIRMWARE;

 *	};

 * };

 */

static int tn40_swnodes_register(struct tn40_priv *priv)

{

	struct tn40_nodes *nodes = &priv->nodes;

	struct pci_dev *pdev = priv->pdev;

	struct software_node *swnodes;

	u32 id;



	id = pci_dev_id(pdev);



	snprintf(nodes->phy_name, sizeof(nodes->phy_name), "ethernet-phy@1");

	snprintf(nodes->mdio_name, sizeof(nodes->mdio_name), "tn40_mdio-%x",

		 id);



	swnodes = nodes->swnodes;



	swnodes[SWNODE_MDIO] = NODE_PROP(nodes->mdio_name, NULL);



	nodes->phy_props[0] = PROPERTY_ENTRY_STRING("compatible",

						    "ethernet-phy-id03a1.b4a3");

	nodes->phy_props[1] = PROPERTY_ENTRY_U32("reg", 1);

	nodes->phy_props[2] = PROPERTY_ENTRY_STRING("firmware-name",

						    AQR105_FIRMWARE);

	swnodes[SWNODE_PHY] = NODE_PAR_PROP(nodes->phy_name,

					    &swnodes[SWNODE_MDIO],

					    nodes->phy_props);



	nodes->group[SWNODE_PHY] = &swnodes[SWNODE_PHY];

	nodes->group[SWNODE_MDIO] = &swnodes[SWNODE_MDIO];

	return software_node_register_node_group(nodes->group);

}



void tn40_swnodes_cleanup(struct tn40_priv *priv)

{

	/* cleanup of swnodes is only needed for AQR105-based cards */

	if (priv->pdev->device == PCI_DEVICE_ID_TEHUTI_TN9510) {

		fwnode_handle_put(dev_fwnode(&priv->mdio->dev));

		device_remove_software_node(&priv->mdio->dev);

		software_node_unregister_node_group(priv->nodes.group);

	}

}



int tn40_mdiobus_init(struct tn40_priv *priv)

{

	struct pci_dev *pdev = priv->pdev;
@@ -129,14 +181,40 @@ int tn40_mdiobus_init(struct tn40_priv *priv) 


	bus->read_c45 = tn40_mdio_read_c45;

	bus->write_c45 = tn40_mdio_write_c45;

	priv->mdio = bus;



	/* provide swnodes for AQR105-based cards only */

	if (pdev->device == PCI_DEVICE_ID_TEHUTI_TN9510) {

		ret = tn40_swnodes_register(priv);

		if (ret) {

			pr_err("swnodes failed\n");

			return ret;

		}



		ret = device_add_software_node(&bus->dev,

					       priv->nodes.group[SWNODE_MDIO]);

		if (ret) {

			dev_err(&pdev->dev,

				"device_add_software_node failed: %d\n", ret);

			goto err_swnodes_unregister;

		}

	}



	tn40_mdio_set_speed(priv, TN40_MDIO_SPEED_6MHZ);

	ret = devm_mdiobus_register(&pdev->dev, bus);

	if (ret) {

		dev_err(&pdev->dev, "failed to register mdiobus %d %u %u\n",

			ret, bus->state, MDIOBUS_UNREGISTERED);

		return ret;

		goto err_swnodes_cleanup;

	}

	tn40_mdio_set_speed(priv, TN40_MDIO_SPEED_6MHZ);

	priv->mdio = bus;

	return 0;



err_swnodes_unregister:

	software_node_unregister_node_group(priv->nodes.group);

	return ret;

err_swnodes_cleanup:

	tn40_swnodes_cleanup(priv);

	return ret;

}



MODULE_FIRMWARE(AQR105_FIRMWARE);

drivers/net/phy/aquantia/aquantia_firmware.c

+4 −3
Original line number Diff line number Diff line
@@ -328,10 +328,11 @@ static int aqr_firmware_load_fs(struct phy_device *phydev) 
	const char *fw_name;

	int ret;



	ret = of_property_read_string(dev->of_node, "firmware-name",

				      &fw_name);

	if (ret)

	ret = device_property_read_string(dev, "firmware-name", &fw_name);

	if (ret) {

		phydev_err(phydev, "failed to read firmware-name: %d\n", ret);

		return ret;

	}



	ret = request_firmware(&fw, fw_name, dev);

	if (ret) {

drivers/net/phy/aquantia/aquantia_main.c

+238 −2
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ 
#define MDIO_AN_VEND_PROV_1000BASET_HALF	BIT(14)

#define MDIO_AN_VEND_PROV_5000BASET_FULL	BIT(11)

#define MDIO_AN_VEND_PROV_2500BASET_FULL	BIT(10)

#define MDIO_AN_VEND_PROV_EXC_PHYID_INFO	BIT(6)

#define MDIO_AN_VEND_PROV_DOWNSHIFT_EN		BIT(4)

#define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK	GENMASK(3, 0)

#define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT	4
@@ -333,6 +334,238 @@ static int aqr_read_status(struct phy_device *phydev) 
	return genphy_c45_read_status(phydev);

}



static int aqr105_get_features(struct phy_device *phydev)

{

	int ret;



	/* Normal feature discovery */

	ret = genphy_c45_pma_read_abilities(phydev);

	if (ret)

		return ret;



	/* The AQR105 PHY misses to indicate the 2.5G and 5G modes, so add them

	 * here

	 */

	linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,

			 phydev->supported);

	linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,

			 phydev->supported);



	/* The AQR105 PHY suppports both RJ45 and SFP+ interfaces */

	linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported);

	linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported);



	return 0;

}



static int aqr105_setup_forced(struct phy_device *phydev)

{

	int vend = MDIO_AN_VEND_PROV_EXC_PHYID_INFO;

	int ctrl10 = 0;

	int adv = ADVERTISE_CSMA;

	int ret;



	switch (phydev->speed) {

	case SPEED_100:

		adv |= ADVERTISE_100FULL;

		break;

	case SPEED_1000:

		adv |= ADVERTISE_NPAGE;

		if (phydev->duplex == DUPLEX_FULL)

			vend |= MDIO_AN_VEND_PROV_1000BASET_FULL;

		else

			vend |= MDIO_AN_VEND_PROV_1000BASET_HALF;

		break;

	case SPEED_2500:

		adv |= (ADVERTISE_NPAGE | ADVERTISE_RESV);

		vend |= MDIO_AN_VEND_PROV_2500BASET_FULL;

		break;

	case SPEED_5000:

		adv |= (ADVERTISE_NPAGE | ADVERTISE_RESV);

		vend |= MDIO_AN_VEND_PROV_5000BASET_FULL;

		break;

	case SPEED_10000:

		adv |= (ADVERTISE_NPAGE | ADVERTISE_RESV);

		ctrl10 |= MDIO_AN_10GBT_CTRL_ADV10G;

		break;

	default:

		return -EINVAL;

	}

	ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, adv);

	if (ret < 0)

		return ret;

	ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, vend);

	if (ret < 0)

		return ret;

	ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, ctrl10);

	if (ret < 0)

		return ret;



	/* set by vendor driver, but should be on by default */

	ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,

			       MDIO_AN_CTRL1_XNP);

	if (ret < 0)

		return ret;



	return genphy_c45_an_disable_aneg(phydev);

}



static int aqr105_config_aneg(struct phy_device *phydev)

{

	bool changed = false;

	u16 reg;

	int ret;



	ret = aqr_set_mdix(phydev, phydev->mdix_ctrl);

	if (ret < 0)

		return ret;

	if (ret > 0)

		changed = true;



	if (phydev->autoneg == AUTONEG_DISABLE)

		return aqr105_setup_forced(phydev);



	ret = genphy_c45_an_config_aneg(phydev);

	if (ret < 0)

		return ret;

	if (ret > 0)

		changed = true;



	/* Clause 45 has no standardized support for 1000BaseT, therefore

	 * use vendor registers for this mode.

	 */

	reg = 0;

	if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,

			      phydev->advertising))

		reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;



	if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,

			      phydev->advertising))

		reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;



	/* Handle the case when the 2.5G and 5G speeds are not advertised */

	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,

			      phydev->advertising))

		reg |= MDIO_AN_VEND_PROV_2500BASET_FULL;



	if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,

			      phydev->advertising))

		reg |= MDIO_AN_VEND_PROV_5000BASET_FULL;



	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,

				     MDIO_AN_VEND_PROV_1000BASET_HALF |

				     MDIO_AN_VEND_PROV_1000BASET_FULL |

				     MDIO_AN_VEND_PROV_2500BASET_FULL |

				     MDIO_AN_VEND_PROV_5000BASET_FULL, reg);

	if (ret < 0)

		return ret;

	if (ret > 0)

		changed = true;



	return genphy_c45_check_and_restart_aneg(phydev, changed);

}



static int aqr105_read_rate(struct phy_device *phydev)

{

	int val;



	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);

	if (val < 0)

		return val;



	if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)

		phydev->duplex = DUPLEX_FULL;

	else

		phydev->duplex = DUPLEX_HALF;



	switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {

	case MDIO_AN_TX_VEND_STATUS1_10BASET:

		phydev->speed = SPEED_10;

		break;

	case MDIO_AN_TX_VEND_STATUS1_100BASETX:

		phydev->speed = SPEED_100;

		break;

	case MDIO_AN_TX_VEND_STATUS1_1000BASET:

		phydev->speed = SPEED_1000;

		break;

	case MDIO_AN_TX_VEND_STATUS1_2500BASET:

		phydev->speed = SPEED_2500;

		break;

	case MDIO_AN_TX_VEND_STATUS1_5000BASET:

		phydev->speed = SPEED_5000;

		break;

	case MDIO_AN_TX_VEND_STATUS1_10GBASET:

		phydev->speed = SPEED_10000;

		break;

	default:

		phydev->speed = SPEED_UNKNOWN;

	}



	return 0;

}



static int aqr105_read_status(struct phy_device *phydev)

{

	int ret;

	int val;



	ret = aqr_read_status(phydev);

	if (ret)

		return ret;



	if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)

		return 0;



	/**

	 * The status register is not immediately correct on line side link up.

	 * Poll periodically until it reflects the correct ON state.

	 * Only return fail for read error, timeout defaults to OFF state.

	 */

	ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PHYXS,

					MDIO_PHYXS_VEND_IF_STATUS, val,

					(FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val) !=

					MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF),

					AQR107_OP_IN_PROG_SLEEP,

					AQR107_OP_IN_PROG_TIMEOUT, false);

	if (ret && ret != -ETIMEDOUT)

		return ret;



	switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {

	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:

		phydev->interface = PHY_INTERFACE_MODE_10GKR;

		break;

	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX:

		phydev->interface = PHY_INTERFACE_MODE_1000BASEKX;

		break;

	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:

		phydev->interface = PHY_INTERFACE_MODE_10GBASER;

		break;

	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:

		phydev->interface = PHY_INTERFACE_MODE_USXGMII;

		break;

	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI:

		phydev->interface = PHY_INTERFACE_MODE_XAUI;

		break;

	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:

		phydev->interface = PHY_INTERFACE_MODE_SGMII;

		break;

	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI:

		phydev->interface = PHY_INTERFACE_MODE_RXAUI;

		break;

	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:

		phydev->interface = PHY_INTERFACE_MODE_2500BASEX;

		break;

	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF:

	default:

		phydev->link = false;

		phydev->interface = PHY_INTERFACE_MODE_NA;

		break;

	}



	/* Read rate from vendor register */

	return aqr105_read_rate(phydev);

}



static int aqr107_read_rate(struct phy_device *phydev)

{

	u32 config_reg;
@@ -911,10 +1144,13 @@ static struct phy_driver aqr_driver[] = { 
{

	PHY_ID_MATCH_MODEL(PHY_ID_AQR105),

	.name		= "Aquantia AQR105",

	.config_aneg    = aqr_config_aneg,

	.get_features	= aqr105_get_features,

	.probe		= aqr107_probe,

	.config_init	= aqr107_config_init,

	.config_aneg    = aqr105_config_aneg,

	.config_intr	= aqr_config_intr,

	.handle_interrupt = aqr_handle_interrupt,

	.read_status	= aqr_read_status,

	.read_status	= aqr105_read_status,

	.suspend	= aqr107_suspend,

	.resume		= aqr107_resume,

},