Commit b7117911 authored by Thierry Reding's avatar Thierry Reding
Browse files

arm64: tegra: Add memory controller on Tegra264 

Link: https://lore.kernel.org/r/20250709231401.3767130-4-thierry.reding@gmail.com


Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 65ef237e

arch/arm64/boot/dts/nvidia/tegra264.dtsi

+53 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
#include <dt-bindings/clock/nvidia,tegra264.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/mailbox/tegra186-hsp.h>

#include <dt-bindings/memory/nvidia,tegra264.h>

#include <dt-bindings/reset/nvidia,tegra264.h>



/ {
@@ -196,6 +197,58 @@ smmu2: iommu@6000000 { 
			dma-coherent;

		};



		mc: memory-controller@8020000 {

			compatible = "nvidia,tegra264-mc";

			reg = <0x00 0x8020000 0x0 0x20000>, /* MC broadcast */

			      <0x00 0x8040000 0x0 0x20000>, /* MC  0 */

			      <0x00 0x8060000 0x0 0x20000>, /* MC  1 */

			      <0x00 0x8080000 0x0 0x20000>, /* MC  2 */

			      <0x00 0x80a0000 0x0 0x20000>, /* MC  3 */

			      <0x00 0x80c0000 0x0 0x20000>, /* MC  4 */

			      <0x00 0x80e0000 0x0 0x20000>, /* MC  5 */

			      <0x00 0x8100000 0x0 0x20000>, /* MC  6 */

			      <0x00 0x8120000 0x0 0x20000>, /* MC  7 */

			      <0x00 0x8140000 0x0 0x20000>, /* MC  8 */

			      <0x00 0x8160000 0x0 0x20000>, /* MC  9 */

			      <0x00 0x8180000 0x0 0x20000>, /* MC 10 */

			      <0x00 0x81a0000 0x0 0x20000>, /* MC 11 */

			      <0x00 0x81c0000 0x0 0x20000>, /* MC 12 */

			      <0x00 0x81e0000 0x0 0x20000>, /* MC 13 */

			      <0x00 0x8200000 0x0 0x20000>, /* MC 14 */

			      <0x00 0x8220000 0x0 0x20000>; /* MC 15 */

			reg-names = "broadcast", "ch0", "ch1", "ch2", "ch3",

				    "ch4", "ch5", "ch6", "ch7", "ch8", "ch9",

				    "ch10", "ch11", "ch12", "ch13", "ch14",

				    "ch15";

			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;

			#interconnect-cells = <1>;



			#address-cells = <2>;

			#size-cells = <2>;



			/* limit the DMA range for memory clients to [39:0] */

			dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;



			emc: external-memory-controller@8800000 {

				compatible = "nvidia,tegra264-emc";

				reg = <0x00 0x8800000 0x0 0x20000>,

				      <0x00 0x8890000 0x0 0x20000>;

				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&bpmp TEGRA264_CLK_EMC>;

				clock-names = "emc";



				#interconnect-cells = <0>;

				nvidia,bpmp = <&bpmp>;

			};

		};



		smmu0: iommu@a000000 {

			compatible = "arm,smmu-v3";

			reg = <0x00 0xa000000 0x0 0x200000>;