Commit b7674ae7 authored by Tao Zhou's avatar Tao Zhou Committed by Alex Deucher
Browse files

drm/amdgu: get RAS retire flip bits for new type of HBM 



Get RAS retire flip bits for HBM with different types in various NPS modes.
Also set flip row bit and MCA R13 bit in PA in different NPS modes.

Signed-off-by: default avatarTao Zhou <tao.zhou1@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9b5b7189

drivers/gpu/drm/amd/amdgpu/umc_v12_0.c

+25 −10
Original line number Diff line number Diff line
@@ -188,25 +188,40 @@ static void umc_v12_0_get_retire_flip_bits(struct amdgpu_device *adev) 
	flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C3_BIT;

	flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_C4_BIT;

	flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R13_BIT;

	flip_bits->flip_row_bit = 13;

	flip_bits->bit_num = 4;

	flip_bits->r13_in_pa = UMC_V12_0_PA_R13_BIT;



	switch (vram_type) {

	case AMDGPU_VRAM_TYPE_HBM:

		/* other nps modes are taken as nps1 */

	if (nps == AMDGPU_NPS2_PARTITION_MODE) {

		flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT;

		flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT;

		flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT;

			flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;

		}



		if (nps == AMDGPU_NPS4_PARTITION_MODE) {

		flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT;

	} else if (nps == AMDGPU_NPS4_PARTITION_MODE) {

		flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT;

		flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT;

		flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT;

			flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;

		flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT;

	}



	switch (vram_type) {

	case AMDGPU_VRAM_TYPE_HBM:

		/* other nps modes are taken as nps1 */

		if (nps == AMDGPU_NPS2_PARTITION_MODE)

			flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;

		else if (nps == AMDGPU_NPS4_PARTITION_MODE)

			flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;



		break;

	case AMDGPU_VRAM_TYPE_HBM3E:

		flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;

		flip_bits->flip_row_bit = 12;



		if (nps == AMDGPU_NPS2_PARTITION_MODE)

			flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;

		else if (nps == AMDGPU_NPS4_PARTITION_MODE)

			flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT;



		break;

	default:

		dev_warn(adev->dev,

drivers/gpu/drm/amd/amdgpu/umc_v12_0.h

+1 −0
Original line number Diff line number Diff line
@@ -62,6 +62,7 @@ 
#define UMC_V12_0_PA_C4_BIT 21

/* row bits in SOC physical address */

#define UMC_V12_0_PA_R0_BIT 22

#define UMC_V12_0_PA_R10_BIT 32

#define UMC_V12_0_PA_R11_BIT 33

#define UMC_V12_0_PA_R12_BIT 34

#define UMC_V12_0_PA_R13_BIT 35