Commit b7a252e8 authored by Marc Zyngier's avatar Marc Zyngier Committed by Oliver Upton
Browse files

arm64: sysreg: Add layout for ICH_MISR_EL2 



The ICH_MISR_EL2-related macros are missing a number of status
bits that we are about to handle. Take this opportunity to fully
describe the layout of that register as part of the automatic
generation infrastructure.

Reviewed-by: default avatarAndre Przywara <andre.przywara@arm.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250225172930.1850838-4-maz@kernel.org


Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
parent 5815fb82

arch/arm64/include/asm/sysreg.h

+0 −5
Original line number Diff line number Diff line
@@ -562,7 +562,6 @@ 


#define SYS_ICH_VSEIR_EL2		sys_reg(3, 4, 12, 9, 4)

#define SYS_ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)

#define SYS_ICH_MISR_EL2		sys_reg(3, 4, 12, 11, 2)

#define SYS_ICH_EISR_EL2		sys_reg(3, 4, 12, 11, 3)

#define SYS_ICH_ELRSR_EL2		sys_reg(3, 4, 12, 11, 5)

#define SYS_ICH_VMCR_EL2		sys_reg(3, 4, 12, 11, 7)
@@ -983,10 +982,6 @@ 
#define SYS_MPIDR_SAFE_VAL	(BIT(31))



/* GIC Hypervisor interface registers */

/* ICH_MISR_EL2 bit definitions */

#define ICH_MISR_EOI		(1 << 0)

#define ICH_MISR_U		(1 << 1)



/* ICH_LR*_EL2 bit definitions */

#define ICH_LR_VIRTUAL_ID_MASK	((1ULL << 32) - 1)

arch/arm64/tools/sysreg

+12 −0
Original line number Diff line number Diff line
@@ -3071,6 +3071,18 @@ Res0 17:5 
Field	4:0	ListRegs

EndSysreg



Sysreg	ICH_MISR_EL2	3	4	12	11	2

Res0	63:8

Field	7	VGrp1D

Field	6	VGrp1E

Field	5	VGrp0D

Field	4	VGrp0E

Field	3	NP

Field	2	LRENP

Field	1	U

Field	0	EOI

EndSysreg



Sysreg	CONTEXTIDR_EL2	3	4	13	0	1

Fields	CONTEXTIDR_ELx

EndSysreg

tools/arch/arm64/include/asm/sysreg.h

+0 −5
Original line number Diff line number Diff line
@@ -558,7 +558,6 @@ 


#define SYS_ICH_VSEIR_EL2		sys_reg(3, 4, 12, 9, 4)

#define SYS_ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)

#define SYS_ICH_MISR_EL2		sys_reg(3, 4, 12, 11, 2)

#define SYS_ICH_EISR_EL2		sys_reg(3, 4, 12, 11, 3)

#define SYS_ICH_ELRSR_EL2		sys_reg(3, 4, 12, 11, 5)

#define SYS_ICH_VMCR_EL2		sys_reg(3, 4, 12, 11, 7)
@@ -979,10 +978,6 @@ 
#define SYS_MPIDR_SAFE_VAL	(BIT(31))



/* GIC Hypervisor interface registers */

/* ICH_MISR_EL2 bit definitions */

#define ICH_MISR_EOI		(1 << 0)

#define ICH_MISR_U		(1 << 1)



/* ICH_LR*_EL2 bit definitions */

#define ICH_LR_VIRTUAL_ID_MASK	((1ULL << 32) - 1)