Commit b7a855f4 authored by Sebastian Brzezinka's avatar Sebastian Brzezinka Committed by Andi Shyti
Browse files

drm/i915/gt: Relocate Gen6 context-specific workaround 



CACHE_MODE_0 register should be saved and restored as part
of the context, not during engine reset. Move the related
workaround (RC_OP_FLUSH_ENABLE) from rcs_engine_wa_init() to
gen6_ctx_workarounds_init() for Gen6 platforms. This ensures the WA
is applied during context initialisation.

CM0_STC_EVICT_DISABLE_LRA_SNB is also Gen6-specific, but it does
not stick when applied in context, so it remains in engine init.

BSPEC: 11322

Signed-off-by: default avatarSebastian Brzezinka <sebastian.brzezinka@intel.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: default avatarKrzysztof Karas <krzysztof.karas@intel.com>
Signed-off-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Link: https://lore.kernel.org/r/f493bab389e51b2faf7c9a439724e9ea9ca04053.1754902406.git.sebastian.brzezinka@intel.com
parent 77a16455

drivers/gpu/drm/i915/gt/intel_workarounds.c

+3 −3
Original line number Diff line number Diff line
@@ -337,6 +337,9 @@ static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, 
				      struct i915_wa_list *wal)

{

	wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING);



	/* WaDisable_RenderCache_OperationalFlush:snb */

	wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);

}



static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine,
@@ -2644,9 +2647,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
				    GEN6_WIZ_HASHING_MASK,

				    GEN6_WIZ_HASHING_16x4);



		/* WaDisable_RenderCache_OperationalFlush:snb */

		wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);



		/*

		 * From the Sandybridge PRM, volume 1 part 3, page 24:

		 * "If this bit is set, STCunit will have LRA as replacement