Unverified Commit b7b07428 authored Jan 20, 2023 by Arnd Bergmann

Merge tag 'stm32-dt-for-v6.2-fixes-1' of...

Merge tag 'stm32-dt-for-v6.2-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/fixes

STM32 DT fixes for v6.2, round 1

Highlights:
-----------

 -STM32MP15:
  - Fix missing chip select phandle in several stm32mp15x based boards.

* tag 'stm32-dt-for-v6.2-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
  ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp151a-prtt1l
  ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp157c-emstamp-argon
  ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp15xx-dhcom-som
  ARM: dts: stm32: Fix qspi pinctrl phandle for stm32mp15xx-dhcor-som

Link: https://lore.kernel.org/r/3fe26bf9-297b-5c78-682b-37fa6d8b6190@foss.st.com


Signed-off-by: Arnd Bergmann <arnd@arndb.de>

parents e2f7096f 175281f8

arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi

+6 −2

Original line number	Diff line number	Diff line
		@@ -101,8 +101,12 @@ &iwdg2 {

		&qspi {
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
		pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
		pinctrl-0 = <&qspi_clk_pins_a
		&qspi_bk1_pins_a
		&qspi_cs1_pins_a>;
		pinctrl-1 = <&qspi_clk_sleep_pins_a
		&qspi_bk1_sleep_pins_a
		&qspi_cs1_sleep_pins_a>;
		reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
		#address-cells = <1>;
		#size-cells = <0>;

arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi

+6 −2

Original line number	Diff line number	Diff line
		@@ -391,8 +391,12 @@ &pwr_regulators {

		&qspi {
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
		pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
		pinctrl-0 = <&qspi_clk_pins_a
		&qspi_bk1_pins_a
		&qspi_cs1_pins_a>;
		pinctrl-1 = <&qspi_clk_sleep_pins_a
		&qspi_bk1_sleep_pins_a
		&qspi_cs1_sleep_pins_a>;
		reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
		#address-cells = <1>;
		#size-cells = <0>;

arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi

+6 −2

Original line number	Diff line number	Diff line
		@@ -428,8 +428,12 @@ &pwr_regulators {

		&qspi {
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
		pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
		pinctrl-0 = <&qspi_clk_pins_a
		&qspi_bk1_pins_a
		&qspi_cs1_pins_a>;
		pinctrl-1 = <&qspi_clk_sleep_pins_a
		&qspi_bk1_sleep_pins_a
		&qspi_cs1_sleep_pins_a>;
		reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
		#address-cells = <1>;
		#size-cells = <0>;

arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi

+6 −2

Original line number	Diff line number	Diff line
		@@ -247,8 +247,12 @@ &pwr_regulators {

		&qspi {
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
		pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>;
		pinctrl-0 = <&qspi_clk_pins_a
		&qspi_bk1_pins_a
		&qspi_cs1_pins_a>;
		pinctrl-1 = <&qspi_clk_sleep_pins_a
		&qspi_bk1_sleep_pins_a
		&qspi_cs1_sleep_pins_a>;
		reg = <0x58003000 0x1000>, <0x70000000 0x200000>;
		#address-cells = <1>;
		#size-cells = <0>;