Commit b7efd229 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-imx-6.14' of... 

Merge tag 'clk-imx-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx

Pull i.MX clk driver updates from Abel Vesa:

 - Fix the i.MX8MP clkout1/2 support by using sys_plln_out instead of
   sys_plln as parents
 - Add 208 MHz and 416 MHz entries to the PLL1416x
 - Fix the i.MX93 provider by adding the SPDIF IPG clock
 - Fix the i.MX93 xcvr DT node clocks by using SPDIF IRP clock instead of
   BUS_WAKEUP
 - Filter out LVDS, MIPI DSI, PXP, FLEXIO and MU clocks to i.MX93 only

* tag 'clk-imx-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
  clk: imx: Apply some clks only for i.MX93
  arm64: dts: imx93: Use IMX93_CLK_SPDIF_IPG as SPDIF IPG clock
  clk: imx93: Add IMX93_CLK_SPDIF_IPG clock
  dt-bindings: clock: imx93: Add SPDIF IPG clk
  clk: imx: pll14xx: Add 208 MHz and 416 MHz entries for PLL1416x
  clk: imx8mp: Fix clkout1/2 support
parents 40384c84 48806be0

arch/arm64/boot/dts/freescale/imx93.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -925,7 +925,7 @@ xcvr: xcvr@42680000 { 
				reg-names = "ram", "regs", "rxfifo", "txfifo";

				interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX93_CLK_BUS_WAKEUP>,

				clocks = <&clk IMX93_CLK_SPDIF_IPG>,

					 <&clk IMX93_CLK_SPDIF_GATE>,

					 <&clk IMX93_CLK_DUMMY>,

					 <&clk IMX93_CLK_AUD_XCVR_GATE>;

drivers/clk/imx/clk-imx8mp.c

+3 −2
Original line number Diff line number Diff line
@@ -399,8 +399,9 @@ static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_r 


static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",

						  "dummy", "dummy", "gpu_pll_out", "vpu_pll_out",

						  "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",

						  "dummy", "dummy", "osc_24m", "dummy", "osc_32k"};

						  "arm_pll_out", "sys_pll1_out", "sys_pll2_out",

						  "sys_pll3_out", "dummy", "dummy", "osc_24m",

						  "dummy", "osc_32k"};



static struct clk_hw **hws;

static struct clk_hw_onecell_data *clk_hw_data;

drivers/clk/imx/clk-imx93.c

+17 −15
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ 


#include "clk.h"



#define IMX93_CLK_END 207

#define IMX93_CLK_END 208



#define PLAT_IMX93 BIT(0)

#define PLAT_IMX91 BIT(1)
@@ -38,6 +38,7 @@ static u32 share_count_sai2; 
static u32 share_count_sai3;

static u32 share_count_mub;

static u32 share_count_pdm;

static u32 share_count_spdif;



static const char * const a55_core_sels[] = {"a55_alt", "arm_pll"};

static const char *parent_names[MAX_SEL][4] = {
@@ -70,8 +71,8 @@ static const struct imx93_clk_root { 
	{ IMX93_CLK_WAKEUP_AXI,		"wakeup_axi_root",	0x0380,	FAST_SEL, CLK_IS_CRITICAL },

	{ IMX93_CLK_SWO_TRACE,		"swo_trace_root",	0x0400,	LOW_SPEED_IO_SEL, },

	{ IMX93_CLK_M33_SYSTICK,	"m33_systick_root",	0x0480,	LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },

	{ IMX93_CLK_FLEXIO1,		"flexio1_root",		0x0500,	LOW_SPEED_IO_SEL, },

	{ IMX93_CLK_FLEXIO2,		"flexio2_root",		0x0580,	LOW_SPEED_IO_SEL, },

	{ IMX93_CLK_FLEXIO1,		"flexio1_root",		0x0500,	LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },

	{ IMX93_CLK_FLEXIO2,		"flexio2_root",		0x0580,	LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },

	{ IMX93_CLK_LPTMR1,		"lptmr1_root",		0x0700,	LOW_SPEED_IO_SEL, },

	{ IMX93_CLK_LPTMR2,		"lptmr2_root",		0x0780,	LOW_SPEED_IO_SEL, },

	{ IMX93_CLK_TPM2,		"tpm2_root",		0x0880,	TPM_SEL, },
@@ -177,10 +178,10 @@ static const struct imx93_clk_ccgr { 
	{ IMX93_CLK_WDOG5_GATE,		"wdog5",	"osc_24m",		0x8400, },

	{ IMX93_CLK_SEMA1_GATE,		"sema1",	"bus_aon_root",		0x8440, },

	{ IMX93_CLK_SEMA2_GATE,		"sema2",	"bus_wakeup_root",	0x8480, },

	{ IMX93_CLK_MU1_A_GATE,		"mu1_a",	"bus_aon_root",		0x84c0, CLK_IGNORE_UNUSED },

	{ IMX93_CLK_MU2_A_GATE,		"mu2_a",	"bus_wakeup_root",	0x84c0, CLK_IGNORE_UNUSED },

	{ IMX93_CLK_MU1_B_GATE,		"mu1_b",	"bus_aon_root",		0x8500, 0, &share_count_mub },

	{ IMX93_CLK_MU2_B_GATE,		"mu2_b",	"bus_wakeup_root",	0x8500, 0, &share_count_mub },

	{ IMX93_CLK_MU1_A_GATE,		"mu1_a",	"bus_aon_root",		0x84c0, CLK_IGNORE_UNUSED, NULL, PLAT_IMX93 },

	{ IMX93_CLK_MU2_A_GATE,		"mu2_a",	"bus_wakeup_root",	0x84c0, CLK_IGNORE_UNUSED, NULL, PLAT_IMX93 },

	{ IMX93_CLK_MU1_B_GATE,		"mu1_b",	"bus_aon_root",		0x8500, 0, &share_count_mub, PLAT_IMX93 },

	{ IMX93_CLK_MU2_B_GATE,		"mu2_b",	"bus_wakeup_root",	0x8500, 0, &share_count_mub, PLAT_IMX93 },

	{ IMX93_CLK_EDMA1_GATE,		"edma1",	"m33_root",		0x8540, },

	{ IMX93_CLK_EDMA2_GATE,		"edma2",	"wakeup_axi_root",	0x8580, },

	{ IMX93_CLK_FLEXSPI1_GATE,	"flexspi1",	"flexspi1_root",	0x8640, },
@@ -188,8 +189,8 @@ static const struct imx93_clk_ccgr { 
	{ IMX93_CLK_GPIO2_GATE,		"gpio2",	"bus_wakeup_root",	0x88c0, },

	{ IMX93_CLK_GPIO3_GATE,		"gpio3",	"bus_wakeup_root",	0x8900, },

	{ IMX93_CLK_GPIO4_GATE,		"gpio4",	"bus_wakeup_root",	0x8940, },

	{ IMX93_CLK_FLEXIO1_GATE,	"flexio1",	"flexio1_root",		0x8980, },

	{ IMX93_CLK_FLEXIO2_GATE,	"flexio2",	"flexio2_root",		0x89c0, },

	{ IMX93_CLK_FLEXIO1_GATE,	"flexio1",	"flexio1_root",		0x8980, 0, NULL, PLAT_IMX93},

	{ IMX93_CLK_FLEXIO2_GATE,	"flexio2",	"flexio2_root",		0x89c0, 0, NULL, PLAT_IMX93},

	{ IMX93_CLK_LPIT1_GATE,		"lpit1",	"bus_aon_root",		0x8a00, },

	{ IMX93_CLK_LPIT2_GATE,		"lpit2",	"bus_wakeup_root",	0x8a40, },

	{ IMX93_CLK_LPTMR1_GATE,	"lptmr1",	"lptmr1_root",		0x8a80, },
@@ -238,10 +239,10 @@ static const struct imx93_clk_ccgr { 
	{ IMX93_CLK_SAI3_GATE,          "sai3",         "sai3_root",            0x94c0, 0, &share_count_sai3},

	{ IMX93_CLK_SAI3_IPG,		"sai3_ipg_clk", "bus_wakeup_root",	0x94c0, 0, &share_count_sai3},

	{ IMX93_CLK_MIPI_CSI_GATE,	"mipi_csi",	"media_apb_root",	0x9580, },

	{ IMX93_CLK_MIPI_DSI_GATE,	"mipi_dsi",	"media_apb_root",	0x95c0, },

	{ IMX93_CLK_LVDS_GATE,		"lvds",		"media_ldb_root",	0x9600, },

	{ IMX93_CLK_MIPI_DSI_GATE,	"mipi_dsi",	"media_apb_root",	0x95c0, 0, NULL, PLAT_IMX93 },

	{ IMX93_CLK_LVDS_GATE,		"lvds",		"media_ldb_root",	0x9600, 0, NULL, PLAT_IMX93 },

	{ IMX93_CLK_LCDIF_GATE,		"lcdif",	"media_apb_root",	0x9640, },

	{ IMX93_CLK_PXP_GATE,		"pxp",		"media_apb_root",	0x9680, },

	{ IMX93_CLK_PXP_GATE,		"pxp",		"media_apb_root",	0x9680, 0, NULL, PLAT_IMX93 },

	{ IMX93_CLK_ISI_GATE,		"isi",		"media_apb_root",	0x96c0, },

	{ IMX93_CLK_NIC_MEDIA_GATE,	"nic_media",	"media_axi_root",	0x9700, },

	{ IMX93_CLK_USB_CONTROLLER_GATE, "usb_controller", "hsio_root",		0x9a00, },
@@ -252,7 +253,8 @@ static const struct imx93_clk_ccgr { 
	{ IMX93_CLK_MQS1_GATE,		"mqs1",		"sai1_root",		0x9b00, },

	{ IMX93_CLK_MQS2_GATE,		"mqs2",		"sai3_root",		0x9b40, },

	{ IMX93_CLK_AUD_XCVR_GATE,	"aud_xcvr",	"audio_xcvr_root",	0x9b80, },

	{ IMX93_CLK_SPDIF_GATE,		"spdif",	"spdif_root",		0x9c00, },

	{ IMX93_CLK_SPDIF_IPG,		"spdif_ipg_clk", "bus_wakeup_root",	0x9c00, 0, &share_count_spdif},

	{ IMX93_CLK_SPDIF_GATE,		"spdif",	"spdif_root",		0x9c00, 0, &share_count_spdif},

	{ IMX93_CLK_HSIO_32K_GATE,	"hsio_32k",	"osc_32k",		0x9dc0, },

	{ IMX93_CLK_ENET1_GATE,		"enet1",	"wakeup_axi_root",	0x9e00, 0, NULL, PLAT_IMX93, },

	{ IMX93_CLK_ENET_QOS_GATE,	"enet_qos",	"wakeup_axi_root",	0x9e40, 0, NULL, PLAT_IMX93, },

drivers/clk/imx/clk-pll14xx.c

+2 −0
Original line number Diff line number Diff line
@@ -56,7 +56,9 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = { 
	PLL_1416X_RATE(700000000U,  350, 3, 2),

	PLL_1416X_RATE(640000000U,  320, 3, 2),

	PLL_1416X_RATE(600000000U,  300, 3, 2),

	PLL_1416X_RATE(416000000U,  208, 3, 2),

	PLL_1416X_RATE(320000000U,  160, 3, 2),

	PLL_1416X_RATE(208000000U,  208, 3, 3),

};



static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {

include/dt-bindings/clock/imx93-clock.h

+1 −0
Original line number Diff line number Diff line
@@ -209,5 +209,6 @@ 
#define IMX91_CLK_ENET2_REGULAR     204

#define IMX91_CLK_ENET2_REGULAR_GATE		205

#define IMX91_CLK_ENET1_QOS_TSN_GATE		206

#define IMX93_CLK_SPDIF_IPG		207



#endif